研究生: |
王禮賜 Wang, Li-Cih |
---|---|
論文名稱: |
多重溝槽式超級接面金氧半場效電晶體設計 The study of Super Junction Power MOSFET by Multi-step Trench Process |
指導教授: |
金雅琴
King, Ya-Chin |
口試委員: |
林榮崇
金雅琴 施教仁 |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering |
論文出版年: | 2012 |
畢業學年度: | 100 |
語文別: | 中文 |
論文頁數: | 57 |
中文關鍵詞: | 超級接面 |
外文關鍵詞: | super junction |
相關次數: | 點閱:2 下載:0 |
分享至: |
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
近年來,能源議題被大家所重視,許多功率元件的研究報告因此被提出,在眾多的功率元件之中,又以超級接面架構的功率元件被廣泛的討論,原因為超級接面具有較低的特徵導通電阻,可以利用此架構特有的耐壓結構來使得功率元件突破矽極限(Silicon-limit)。
在製造超級接面功率金氧半場效電晶體方法中,目前主要的方法有兩種,第一種為多重磊晶成長法,第二種為溝槽填充法,溝槽填充法比起多重磊晶成長法製作要來得容易且節省成本,但是溝槽填充法無法製作出一個較高的深寬比的P/N結構,同時,且在填充單晶矽時容易有空洞產生,造成元件特性不穩定,因此,若想用溝槽填充法來製作出600V超級接面金氧半場效電晶體在製程技術上將面對較大的挑戰。
本篇論文提出了一個新的製作超級接面金氧半場效電晶體的方法,稱為「多重溝槽填充法」,利用此種技術製作超級接面不僅可以有效緩解深寬比的問題,也改善了此元件對於製程參數變異的承受能力。利用多重溝槽填充法來製作超級接面,同時也提供了一個較高的製作自由度,利用這個自由度來調整溝槽的次數、深度,以及每次溝槽填充的濃度,在製造超級接面時,經由調整這些變因,來達到最佳化設計主元件及周邊耐壓結構的效果。
In recent years, the power device research is widely proposed when the energy issues become more important. In many power device component the super junction structure power device is widely discussed because this device can reduce the specific on-resistance of the power MOSFETs to below the Si-Limit.
Several methods of fabricating super junction in power MOSFETs has been proposed, such as, multi-step epitaxial growth and trench filling technique. The trench filling method is generally easier and less costly than the epitaxial growth. However, it is very difficult to realize high-aspect-ratio P/N pillars though conventional trench filling technique.
In this paper, we propose the multi-step trenching/filling technique to implement high-aspect-ratio super junction structure. The proposed the multi-trench process can not only effectively alleviate the deep trench filling problem, but also provide better process margin in the implementation of super junction power devices. This multi-trench process allows additional design freedom in the number of trench layers and doping concentration in each layer, which can lead to better breakdown performance in both the main and termination regions.
參考文獻
[1] B.Murari, F.Bertotti, and G.A.Vignola, “Smart Power ICs”.
[2] Jun Sakakibara, et.al, “600V-class Super Junction MOSFET with High Aspect Ratio P/N Columns Structure”, Proc. Intl. Symp. Power Semiconductor Devices & Integrated Circuits, 2008
[3] Chen X.B., Mawby P.A., Board K., Salama C.A.T, “Theory of a novel voltage-sustaining layer for power devices”, Microelectronics Journal, pp. 1005 - 1011, 1998.
[4] Tatsuhiko Fujihira, “Theory of Semiconductor Super junction Devices”, JJAP, pp. 6254-6262, 1997.
[5] P. N. Kondekar, M. B. Patil, and C. D. Parikh, “Analysis and design of super junction power MOSFET: CoolMOSTM for improved on resistance and breakdown voltage using theory of novel voltage sustaining layer,” in Proc. MIEL, vol. 1, 2002, pp. 209–212.
[6] Liang Y.C., Gan K.P., Samudra G.S., “Oxide-bypassed VDMOS (OBVDMOS): an alternative to super junction high voltage MOS power devices, Electron Device Letters”, Vol. 22, pp. 407-409, 2001.
[7] G. Deboy, M. Marz, J. P. Stengl, H. Strack, J. Tihanyi, and H. Weber,“A new generation of high voltage MOSFETs breaks the limit line of silicon,” in IEDM Tech. Dig., 1998, pp. 683–685.
[8] T. Kobayashi, H. Abe, Y. Niimura, T. Yamada, A. Kurosaki, T. Hosen, and T. Fujihira, “High-Voltage Power MOSFETs Reached Almost to the Silicon Limit”, Proc. Intl. Symp. Power Semiconductor Devices Integrated Circuits, pp. 435-438, 2001
[9] M.F.Lee, “The Simulation and Design of 200V Lateral Semiconductor Power Devices”
[10] A. Teramoto, H. Umeda, K. Azamawari', K. Kobayashi', K. Shiga, J. Komori, Y. Ohno, and H. Miyoshi “Study of Oxide Breakdown under Very Low Electric Field”, IEEE,1999
[11] D. Coe, patent EP 0053854, US 4,754.3 IO
[12] M. H. Kim, J. J. Kim, Y. S. Choi, C.K. Jeon, S.L. Kim, H.S. Kang and C.S. Song, ”A Low On Resistance 700V Charge Balanced LDMOS with Intersected WELL Structure”, Proc. Intl. Symp. Power Semiconductor Devices &Integrated Circuits 2003, pp220-223
[13] Ettore Napoli, Han Wang, and Florin Udrea, “The Effect of Charge Imbalance on Super junction Power Devices: An Exact Analytical Solution”, IEEE EDL, VOL. 29, NO. 3, 2008.
[14] T. Minato, T. Nitta, A. Uenisi, M. Yano, M. Harada, and S. Hine, “Which is cooler, Trench or Multi- Epitaxy?,” Proc. Intl. Symp. Power Semiconductor Devices & Integrated Circuits, 2000.
[15] S. Iwamoto, K. Takahashi, H. Kuribayashi, S. Wakimoto, K. Mochizuki, and H. Nakazawa, ”Above 500V class Super junction MOSFETs Fabricated by Deep Trench Etching and Epitaxial Growth,” Proc. Intl. Symp. Power Semiconductor Devices & Integrated Circuits, 2005
[16] Syotaro Ono, ISPSD, May 27-30, 2007.
[17] Jun Sakakibara, ISPSD, May 18-22, 2008.
[18] A. Sugi,ISPSD, May 18-22, 2008Oralando, FL
[19] Shoichi Yamauchi, ISPSD, June 4-8, 2006.
[20] Y. Onishi*, IEEE 2002.