使用同步電腦輔助設計工具於非同步電路前段設計流程

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研究生：	葉松艷 Yeh, Sung-Yen
論文名稱：	使用同步電腦輔助設計工具於非同步電路前段設計流程 An Asynchronous Circuit Front-end Design Flow with Synchronous CAD Tools
指導教授：	張彌彰 Chang, Mi-Chang
口試委員:	洪浩喬 Hong, Hao-Chiao 謝志成 Hsieh, Chih-Cheng
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2011
畢業學年度：	100
語文別：	中文
論文頁數：	70
中文關鍵詞：	非同步電路設計流程、非同步電路、數位積體電路設計
外文關鍵詞：	asynchronous circuit design flow, asynchronous circuit, digital IC design
相關次數：	點閱：3 下載：0
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在製程技術演進至深次微米的今日，數位積體電路設計為了維持良好時脈訊號所花費的成本將愈顯沉重。非同步電路直接免除時脈訊號，使得電路運行更有效率。在這篇論文中，我們提出了一種非同步電路的實現方法，並且採用較普遍的商業電腦輔助設計軟體及同步電路元件庫。彌補現有非同步電路設計流程上的不足及限制。現有的非同步電路設計流程與同步電路設計流程大相逕庭，需要設計者重新學習不熟悉的並行處理程式語言及非同步電路合成工具，並且需要額外的元件庫支援。所提出的非同步設計方法以GALS (Globally Asynchronous Locally Synchronous)系統為基本架構，將各區塊電路模組化並組合成為非同步電路，容許對各區塊做更深入的研究及改進。此外，現有的合成工具並不適合用於非同步電路的設計，因此我們指出了同步合成工具應用於非同步電路的不利處，讓未來電路合成工具的設計能夠對非同步電路提供更多的支援。
在非同步電路的運作上，我們分別使用單級與多級的觀點分析效能，並且指出多級電路中，資料相依性所導致的阻塞(blocking)及飢餓(starvation)現象。在論文最後，將非同步電路及同步電路的效能、面積、能量消耗及模組性做了一個完整的比較。

As the manufacturing technology progresses to deep sub-micron nodes, people must make more efforts to keep better clock signal in digital integrated circuit design than ever. Asynchronous circuits directly remove the clock signal, and make circuit operate more efficiently. In this thesis, we developed an asynchronous design implementation approach which adopts commercial computer aided design tools and synchronous cell libraries, in an attempt to remove the deficiency and restrictions in current asynchronous design flows. Most of current asynchronous design flows are different with synchronous standard flows. They need the support of additional cell libraries, and designers be reeducated for unfamiliar programming language and tools. The proposed asynchronous implementation approach is based on globally asynchronous locally synchronous (GALS) system. All the building blocks are separated and allow individual improvement and modifications. As a result of our research, we found that current synthesis tools are not suitable for asynchronous circuits, and thus we pointed the shortcomings of synchronous synthesis tools as applying to asynchronous designs. We hope that synthesis tools can be improved for the use of asynchronous IC design in the future.
To measure the performance of the proposed asynchronous circuits, we analyzed the timing in single-stage and multiple-stage pipeline configurations, and pointed the phenomenon of blocking and starvation due to data dependency in multiple-stage circuits. At the end of thesis, full comparisons of synchronous and asynchronous designs in performance, area, energy, and modularity are carried out.

摘要    i
Abstract    ii
誌謝    iii
Contents    iv
List of Figures    vi
List of Tables    viii
Chapter 1 Introduction    1
1.1 Motivation    1
1.2 Organization of thesis    2
Chapter 2 Basic Concepts and Related Works    3
2.1 Asynchronous circuit    3
2.1.1 Communication channels    4
2.1.2 Handshaking protocols    5
2.1.3 Data representations    7
2.1.4 Data completion signals    9
2.1.5 C-element    11
2.2 GALS system    13
2.3 Related works    15
Chapter 3 Design Implementation    19
3.1 Asynchronous design architecture    19
3.1.1 Floating-point multiplier    20
3.1.2 Asynchronous wrapper    22
3.1.3 Done signal    23
3.1.4 Inter-block data latches    26
3.1.5 Dummy stages    27
3.2 Synchronous design architecture    28
3.3 Implementation issues    28
3.3.1 Design partitions    28
3.3.2 Synthesis flow    30
3.3.3 Synthesis limitations    32
3.3.4 Multi-path communications    36
Chapter 4 Timing Analysis    41
4.1 Operation time of single-stage asynchronous circuit    41
4.2 Operation time of multiple-stage asynchronous circuit    42
4.3 Impact of inter-block latches    44
4.4 Steal time    45
4.5 Synchronous design timing overhead    46
Chapter 5 Comparisons    48
5.1 Throughput and latency    48
5.2 Area    51
5.3 Energy dissipation    54
5.4 Modularity and variation tolerance    56
Chapter 6 Conclusions and Future Works    58
6.1 Conclusions    58
6.2 Future works    58
References    60
Appendix A    Design Guide    63
Appendix B    Script Files Example    66

                                

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