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研究生: 鍾家旺
Chung, Jia-Wang
論文名稱: 基於PQEMU中斷控制器設計
Interrupt Controller Design Based on PQEMU
指導教授: 鍾葉青
Chung, Yeh-Ching
口試委員: 徐慰中
Hsu, Wei-Chung
洪士灝
Hung, Shih-Hao
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 資訊工程學系
Computer Science
論文出版年: 2012
畢業學年度: 100
語文別: 英文
論文頁數: 27
中文關鍵詞: QEMUPQEMU系統模擬器多執行緒中斷控制器競賽情況
外文關鍵詞: QEMU, PQEMU, system emulator, multi-thread, interrupt controller, race condition
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  • QEMU是一個可以模擬多個平台的系統模擬器。QEMU雖然可以模擬多核心,但他只能循序執行方式模擬CPU。所以沒有發揮底層多核心的機器架構。PQEMU是設計成多執行緒的QEMU,讓模擬器充份發輝多核心硬體的較能。目前PQEMU只能模擬目標ARM 平台。我們把模擬目標x86_64平台移植到PQEMU內。x86_64平台可以支援到255核心。由於PQEMU是多個執行緒同時執行。由於目前的PQEMU對中斷控制器沒有做有較保護,所以當有2個或以上的執行緒同時對中斷控制器操作時會發生競賽情況。所以為了避免發生競賽情況我們設計了2種設計方案,PQEMU-BUS和PQEMU-LOCKS。為了評估這設計,我們在Dell PowerEdge R910機器上分別用QEMU,PQEMU-BUS和PQEMU-LOCKS來模擬x86_64平台,並測量中斷延遲。由於QEMU模擬CPU超過16 cores時啟動Linux作業系統失敗,所以QEMU部份只量測到16 cores。PQEMU-BUS和PQEMU-LOCKS部份量測到255 cores。從測量結果顯示, 在模擬16 cores下PQEMU-BUS和QEMU-LOCKS的外部裝置中斷延遲比QEMU分別減少6.08%和45.92%。PQEMU-BUS和QEMU-LOCKS的CPU之間的中斷延遲比QEMU分別減少99.23%和99.71%。在模擬255 cores下,PQEMU-LOCKS的外部裝置中斷延遲和CPU之間的中斷延遲比PQEMU-BUS分別減少30.49%和43.44%。結果可看出這2個設計不只能避免競賽情況,而且對中斷延遲的減少也有幫助。從結果也可看出PQEMU-LOCKS的設計比PQEMU-BUS設計更能減少中斷延遲。


    QEMU is a system emulator that can emulate multiple platforms. Although QEMU can simulate the multi-core, but is round robin sequential execution in single thread, so can’t use advantage of underlying multi-core hardware. PQEMU is designed the multi-thread QEMU, so can use advantage of underlying multi-core hardware. Currently PQEMU emulator support target ARM platform. We ported target x86_64 platform to PQEMU. X86_64 platform support up to 255 cores emulation. PQEMU all threads concurrently execution. Currently PQEMU do not protect interrupt controller, so 2 or more threads to access interrupt controller, can cause race condition. We will implement two kinds of design avoid race condition, in PQEMU. These two kinds of design are PQEMU-BUS and PQEMU-LOCKS. To evaluate the design, we emulate a target x86_64 platform by separately running QEMU, PQEMU-BUS and PQEMU-LOCKS on Dell PowerEdge R910 machine, and measure them interrupt latency. QEMU emulating more than 16 cores, will not booting Linux operating system. So, QEMU measure to 16 cores. PQEMU-BUS and PQEMU-LOCKS measure to 255 cores. The experimental results show that in emulation 16 cores, PQEMU-BUS and PQEMU-LOCKS external interrupt latency had separately decreased 6.08% and 45.92% compared to QEMU. PQEMU-BUS and PQEMU-LOCKS interprocessor interrupt latency had separately decreased 99.23% and 99.71% compared to QEMU. In emulation 255 cores, PQEMU-LOCKS external interrupt latency and interprocessor interrupt latency had separately decreased 30.49% and 43.44% compared to PQEMU-BUS. The results show that the two designs avoid the race condition, and the decreased interrupt latency. The results show, PQEMU-LOCKS interrupt latency less than PQEMU-BUS.

    Chapter 1 Introduction 1 Chapter 2 Related Work 3 Chapter 3 Background 5 3.1 APIC Architecture 5 3.1.1 IOAPIC 6 3.1.2 LAPIC 6 3.1.3 LAPIC interrupt handling flow 8 3.2 QEMU 9 3.2.1 I/O Interrupt Delivery 9 3.2.2 Emulation of IOAPIC 10 3.2.3 Emulation of LAPIC 11 3.3 PQEMU Emulation of APIC 12 3.4 PQEMU Emulation of APIC Problem 12 Chapter 4 Design And Implementation 14 4.1 Emulation BUS Design for APIC 14 4.1.1 Send Interrupt to BUS 15 4.1.2 Receive Interrupt from BUS 16 4.1.3 Local Timer 17 4.2 LOCKS Design for APIC 18 Chapter 5 Experimental Results 20 5.1 Measure External Interrupt Latency 20 5.2 Measure Interprocessor Interrupt Latency 22 Chapter 6 Conclusions and Future Work 25 Reference 27

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