本論文探討具有低壓操作電壓特性的蕭特基奈米線電荷捕捉式快閃記憶體其製程製作與量測分析，此元件利用蕭特基源/汲極接面增強熱電子電洞的生成，以提升元件在寫入抹除時的效能。於製程製作上，嘗試使用兩種不同流程方式來進行電荷捕捉式快閃記憶體的奈米線通道製作。實驗過程發現，以乾式蝕刻製作法較能確保製程的穩定性與控制性。於量測分析上，進行不同溫度時電荷捕捉式快閃記憶體的電性量測分析。量測結果顯示，在變溫環境操作下，蕭特基矽奈米線電荷捕捉式快閃記憶體仍保有良好的電性曲線與可靠性表現。

This thesis experimentally explores the process fabrication and measurement characterization of Schottky barrier nanowire charge trapping memories. Two different types of hard-mask lithography were examined to fabricate the gate-all-around nanowire structure. In cell characterization, this work studies the cell reading, programming, and erasing at room and higher temperatures. Reliability characterization in cycling endurance and data retention are also investigated. The results show that the high-temperature Schottky barrier nanowire charge trapping cells preserve good electrical characteristics.

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