簡易檢索 / 詳目顯示

研究生: 吳伯濬
Wu, Po Chun
論文名稱: 一個具帶冗餘位之多通道時間交錯式連續漸進式類比數位轉換器
Time-interleaved Successive-Approximation Analog-to-Digital Converter with Redundancy
指導教授: 朱大舜
Chu, Ta Shun
口試委員: 吳仁銘
王毓駒
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2016
畢業學年度: 104
語文別: 中文
論文頁數: 78
中文關鍵詞: 帶冗餘位多通道時間交錯式連續漸進式類比數位轉換器
外文關鍵詞: Redundancy, Time-interleaved, Successive-Approximation Analog-to-Digital
相關次數: 點閱:2下載:0
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • 近年來,攜帶式電子設備的發展日益蓬勃,無線通訊技術的進步大大的改善人們的生活,隨著這些科技不斷的進步,類比數位轉換器在數位時代裡扮演著重要的角色,因為它是類比訊號與數位訊號的主要媒介,能夠將大自然的類比訊號轉換成數位訊號,再將其數位資料交由後級的電路處理,因此類比數位轉換器的效能會大大的影響整個系統的品質,有了轉換器的出現,而使得科技發展更加訊速。隨著資料傳遞量的增加以及對速度的需求,現今有許多不同類型的類比數位轉換器,不斷的在操作速度與解析度上做更近一步的改良,故如何達到高解析度、高取樣速率的類比數位轉換器是非常重要的。

    本論文介紹帶冗餘位演算法、多通道時間交錯式以及連續漸進式類比數位轉換器。連續漸進式類比數位轉換器具有面積及功耗較小的優點,因此由傳統的連續漸進式類比數位轉換器來做修改,藉由帶冗餘位使整個類比數位轉換器具有修正錯誤的能力,來使電路更加的穩定,最後再透過多通道時間交錯式來使整個系統具有更高的取樣速度。

    最後本論文完成了一個具有帶冗餘位之多通道時間交錯式連續漸進式類比數位轉換器,它的規格為10位元,每秒取樣四億次,我們使用台積電65奈米製程模擬設計,模擬結果有效為元為10.08,訊號與雜訊諧波比為62.46dB,平均消耗功率為9.38mW。


    In recent years, the portable electronic device industry has been highly prosperous. The advance in wireless communication technology has dramatically improved people's lives. As the technologies progress constantly, analog-to-digital converter starts to play an important role in the era of digital. Analog-to-digital converter can convert nature signals into digital signals, then send the digital data to post-stage circuit. Thanks to the invention of the converts, technologies progress rapidly in these years. With the increase of the amount of data transmission and the growing demand of high-speed transmission, how to achieve high resolution and high sample rate analog-to-digital converter becomes one of the main issues.
    This thesis introduces algorithms with Redundancy, multi-channel time-interleaved and successive-approximation analog-to-digital converter. Eventually, we have completed a multi-channel time-interleaved successive-approximation analog-to-digital converter with redundancy. Its specifications is 10bits and sampling rate is 400MS/s. We used TSMC 65 nm CMOS process to do the simulation design. This design achieves signal to noise and distortion ratio of 62.46dB, equivalent to the effective number of bits 10.08. The average power consumption is 9.38mW.

    目錄 中文摘要 i Abstract(英文摘要) ii 目錄 iii 圖目錄 vii 表目錄 x 第一章 簡介及研究背景介紹 1 1.1 研究動機(Motivation) 1 1.2 論文章節架構介紹 2 1.3 類比數位轉換器的種類介紹 3 1.3.1 連續漸進式類比數位轉換器(SAR ADC) 3 1.3.2 快閃式類比數位轉換器(Flash ADC) 5 1.3.3 管線式類比數位轉換器(Pipeline ADC) 6 1.4 類比數位轉換器參數 7 1.4.1 奈奎斯特取樣定理(Nyquist Rate) 7 1.4.2 取樣率(Sampling Rate) 8 1.4.3 解析度(Resolution) 8 1.4.4 精確度(Accuracy) 8 1.4.5 最小有效位元(Least Signification Bit) 8 1.4.6 量化誤差(Quantization Error) 9 1.4.7 偏移誤差(Offset Error) 11 1.4.8 增益誤差(Gain Error) 11 1.4.9 微分非線性度(Differential Nonlinearity , DNL) 12 1.4.10 積分非線性度(Integral Nonlinearity , INL) 13 1.4.11遺失碼(Missing Code) 15 1.4.12訊號雜訊比(Signal-to-Noise Ratio) 16 1.4.13 訊號雜訊諧波比(Signal-to-Noise and Distortion Ratio) 16 1.4.14 有效位元數(Effective Number of Bits) 17 1.4.15 無雜訊動態範圍(Spurious Free Dynamic Range) 18 1.4.16 動態範圍(Dynamic Range) 19 1.4.17 總諧波失真(Total Harmonic Distortion) 19 1.4.18 有效解析度頻寬(Effective Resolution Bandwidth) 20 1.4.19 參數總結 20 第二章 連續漸進式類比數位轉換器 21 2.1 連續漸進式類比數位轉換器 21 2.1.1 同步與非同步 21 2.1.2 單端與雙端 22 2.1.3 電容切換演算法 24 2.1.3.a 傳統式電容切換演算法 24 2.1.3.b 單調性電容切換演算法 26 2.1.3.c 電容拆半切換演算法 27 2.2 連續漸進式類比數位轉換器子電路設計 29 2.2.1 取樣保持電路(Sample and Hold) 29 2.2.1.a 電路原理及介紹 29 2.2.1.b 設計上應注意的重點 31 2.2.1.c 電路實作 34 2.2.2 比較器(Comparator) 35 2.2.2.a 電路原理 35 2.2.2.b 設計上應注意的重點 36 2.2.2.c 電路實作 37 2.2.3電容式數位類比轉換器(Capacitor DAC) 38 2.2.3.a電容式數位類比轉換器種類介紹 38 2.2.3.b電路實作 39 2.2.4時脈產生器(Clock Generator) 41 2.2.5連續漸進式邏輯電路(SAR Logic) 41 2.2.6 100MS/s 10bits連續漸進式類比數位轉換器模擬結果 42 第三章 帶冗餘位連續漸進式類比數位轉換器 44 3.1 連續漸進式類比數位轉換器所遇到的困難 44 3.1.1 靜態誤差(Static error) 44 3.1.1.a 電容的不匹配(Capacitor mismatch) 45 3.1.1.b 偏移誤差(Offset error) 46 3.1.2 動態誤差(Dynamic error) 47 3.2 帶冗餘位簡介 47 3.2.1 非二分法搜尋(Non-binary search) 48 3.2.2 忍錯範圍 51 3.2.3 可修正的條件 53 3.2.4 帶冗餘位的量 54 3.2.5 基底γ的選定 54 3.2.5.a 電容不匹配 56 3.2.5.b DAC穩定時間 57 3.2.6 切換次數M的選定 59 3.2.7 設計帶冗餘位的流程 59 3.3 65奈米10位元每秒一億次取樣帶冗餘位演算法實作 61 3.3.1 帶冗餘位連續漸進式類比數位轉換器之電容分佈 64 3.4 帶冗餘位連續漸進式類比數位轉換器模擬結果 65 第四章 多通道時間交錯次類比數位轉換器 67 4.1 多通道時間交錯的非理想效應 67 4.1.1 Offset Mismatch Effect 67 4.1.2 Gain Mismatch Effect 69 4.1.3 Clock Timing Error Effect 70 4.2 電路介紹 73 4.3 模擬結果 74 第五章 結論與未來發展 76 參考文獻 77

    [1]C.C. Liu, et al, ‘‘A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure,’’ IEEE J. Solid-State Circuits, vol.45, no. 4, Apr. 2010, pp. 731-740.
    [2]R. H. Walden, “Analog-to-digital converter survey and analysis,” IEEE J.Sel. Areas Commun., vol. 17, no. 4, pp. 539-550, Apr. 1999.
    [3]C.C. Liu, et al., “A 1V 11fJ/conversion-step 10bit 10MS/s Asynchronous SAR ADC in 0.18μm CMOS,” IEEE Symposium on VLSI Circuits, pp. 241-242, June 2010.
    [4]G.Y. Huang, C.C. Liu, Y.-Z. Lin, and S.J. Chang, "A 10-bit 12-MS/s successive approximation ADC with 1.2-pF input capacitance," in IEEE ASSCC Dig. Tech. Papers, pp. 157-160, November 2009.
    [5]R. Kapusta et al., “A 14b 80 MS/s SAR ADC With 73.6 dB SNDR in 65 nm CMOS,” IEEE J. Solid-State Circuits, vol. 48, no. 12, pp. 3059-3066, Dec. 2013.
    [6]P. M. Figueiredo and J. C. Vital, "Kickback noise reduction techniques for CMOS latched comparators", IEEE Transactions on Circuits and Systems II: Express Briefs, vol.53, no.7, pp. 541-545, 2006.
    [7]D. Aksin, M. Al-Shyoukh, and F. Maloberti, "Switch Bootstrapping for Precise Sampling Beyond Supply Voltage", IEEE Journal of Solid State Circuits, pp. 1938-1943, Aug.2006.
    [8]M. Yoshioka, K. Ishikawa, T. Takayama, and S. Tsukamoto, “A 10-b 50 MS/s 820-uW SAR ADC with on-chip digital calibration,” IEEE ISSCC Dig. Tech. Papers, 2010, pp. 384-385.
    [9]A. H. Chang, H. S. Lee and D. Boning, “A 12b 50MS/s 2.1mW SAR ADC with redundancy and digital background calibration,” ESSCIRC (ESSCIRC), 2013 roceedings of the, Bucharest, 2013, pp. 109-112.
    [10]F. Kuttner, “A 1.2V 10b 20MSample/s Non-Binary Successive Approximation ADC in 0.13_m CMOS,” IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), vol. 1, pp. 176-177, 2002.
    [11]T. Waho, “Non-binary successive approximation analog-to-digital converters:A survey,” in Proc. IEEE Int. Symp. Multiple-Valued Logic(ISMVL), 2014, pp. 73-78
    [12]T. Ogawa, H. Kobayashi, Y. Takahashi, N. Takai, M. Hotta, H. San, T. Matsuura, A. Abe, K. Yagi, T. Mori, "SAR ADC Algorithm with Redundancy and Digital Error Correction", IEICE Trans. Fundamentals, vol.E93-A, no.2 (Feb. 2010).
    [13]T. Ogawa, H. Kobayashi, M. Hotta, Y. Takahashi, H. San, N. Takai, "SAR ADC Algorithm with Redundancy", IEEE Asia Pacific Conference on Circuits and Systems, Macao, China, pp.268-271 (Nov. 2008).
    [14]B. Murmann, “On the use of redundancy in successive approximation A/D converters,” in Proc. IEEE Int. Conf. Sampling Theory and Applications (SampTA), 2013, pp. 1–4
    [15]M. Hesener, T. Eichler, A. Hanneberg, D. Herbison, F. Kuttner, and H. Wenske, “A 14b 40MS/s Redundant SAR ADC with 480MHz Clock in 0.13_m CMOS,” IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 248-249, Feb. 2007.
    [16]N. Kurosawa, H. Kobayashi, K. Maruyama, H. Sugawara, and K. Kobayashi, “Explicit analysis of channel mismatch effects in time-interleaved ADC systems,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 48, no. 3, pp. 261–271, Mar. 2001.
    [17]S. M. Louwsma, A. J. M. Van Tuijl, M. Vertregt, and B. Nauta, “A 1.35 GS/s, 10 b, 175 mW time-interleaved AD converter in 0.13um CMOS,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 778–786, Apr. 2008.
    [18]K. C. Dyer et al. “A digital background calibration technique for time-interleaved analog-to-digital converters”, IEEE J. Solid-State Circuits, vol. 33, Dec. 1998, pp. 1904-1911.
    [19]Jamal, S.M. et al. “A 10-b 120-msample/s time-interleaved analog-to-digital converter with digital background calibration”, IEEE J. Solid-State Circuits, vol.37, Dec. 2002, pp. 1618- 1627.
    [20]C.-Y. Wang and J.-T. Wu, “A background timing-skew calibration technique for time-interleaved analog-to-digital converters,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 4, pp. 299–303, Apr. 2006.
    [21]B. Razavi, Design of Analog CMOS Integrated Circuit. Boston, MA: McGraw-Hill, 2001.

    無法下載圖示 全文公開日期 本全文未授權公開 (校內網路)
    全文公開日期 本全文未授權公開 (校外網路)
    全文公開日期 本全文未授權公開 (國家圖書館:臺灣博碩士論文系統)
    QR CODE