研究生: |
吳伯濬 Wu, Po Chun |
---|---|
論文名稱: |
一個具帶冗餘位之多通道時間交錯式連續漸進式類比數位轉換器 Time-interleaved Successive-Approximation Analog-to-Digital Converter with Redundancy |
指導教授: |
朱大舜
Chu, Ta Shun |
口試委員: |
吳仁銘
王毓駒 |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
論文出版年: | 2016 |
畢業學年度: | 104 |
語文別: | 中文 |
論文頁數: | 78 |
中文關鍵詞: | 帶冗餘位 、多通道時間交錯式 、連續漸進式類比數位轉換器 |
外文關鍵詞: | Redundancy, Time-interleaved, Successive-Approximation Analog-to-Digital |
相關次數: | 點閱:2 下載:0 |
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近年來,攜帶式電子設備的發展日益蓬勃,無線通訊技術的進步大大的改善人們的生活,隨著這些科技不斷的進步,類比數位轉換器在數位時代裡扮演著重要的角色,因為它是類比訊號與數位訊號的主要媒介,能夠將大自然的類比訊號轉換成數位訊號,再將其數位資料交由後級的電路處理,因此類比數位轉換器的效能會大大的影響整個系統的品質,有了轉換器的出現,而使得科技發展更加訊速。隨著資料傳遞量的增加以及對速度的需求,現今有許多不同類型的類比數位轉換器,不斷的在操作速度與解析度上做更近一步的改良,故如何達到高解析度、高取樣速率的類比數位轉換器是非常重要的。
本論文介紹帶冗餘位演算法、多通道時間交錯式以及連續漸進式類比數位轉換器。連續漸進式類比數位轉換器具有面積及功耗較小的優點,因此由傳統的連續漸進式類比數位轉換器來做修改,藉由帶冗餘位使整個類比數位轉換器具有修正錯誤的能力,來使電路更加的穩定,最後再透過多通道時間交錯式來使整個系統具有更高的取樣速度。
最後本論文完成了一個具有帶冗餘位之多通道時間交錯式連續漸進式類比數位轉換器,它的規格為10位元,每秒取樣四億次,我們使用台積電65奈米製程模擬設計,模擬結果有效為元為10.08,訊號與雜訊諧波比為62.46dB,平均消耗功率為9.38mW。
In recent years, the portable electronic device industry has been highly prosperous. The advance in wireless communication technology has dramatically improved people's lives. As the technologies progress constantly, analog-to-digital converter starts to play an important role in the era of digital. Analog-to-digital converter can convert nature signals into digital signals, then send the digital data to post-stage circuit. Thanks to the invention of the converts, technologies progress rapidly in these years. With the increase of the amount of data transmission and the growing demand of high-speed transmission, how to achieve high resolution and high sample rate analog-to-digital converter becomes one of the main issues.
This thesis introduces algorithms with Redundancy, multi-channel time-interleaved and successive-approximation analog-to-digital converter. Eventually, we have completed a multi-channel time-interleaved successive-approximation analog-to-digital converter with redundancy. Its specifications is 10bits and sampling rate is 400MS/s. We used TSMC 65 nm CMOS process to do the simulation design. This design achieves signal to noise and distortion ratio of 62.46dB, equivalent to the effective number of bits 10.08. The average power consumption is 9.38mW.
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