簡易檢索 / 詳目顯示

研究生: 陸志豪
Liu, Chih-Hao
論文名稱: High-Throughput Switch Network Architecture Applied for MIMO Detector and Multi-Mode QC-LDPC Decoder
應用於多輸入多輸出信號偵測與多模QC-LDPC解碼器之高速網路交換器架構
指導教授: 許雅三
Hsu, Yarsun
李鎮宜
Lee, Chen-Yi
口試委員: 吳誠文
Wu, Cheng-Wen
張慶元
Chang, T.-Y.
謝明得
Shieh, Ming-Der
張錫嘉
Chang, Hsie-Chia
蔡佩芸
Tsai, Pei-Yun
吳安宇
Wu, Andy
學位類別: 博士
Doctor
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2011
畢業學年度: 99
語文別: 英文
論文頁數: 55
中文關鍵詞: 交換器解碼器球型網路交換器多輸入多輸出
外文關鍵詞: LDPC, MIMO, swicth, detetcor, sphere decoder
相關次數: 點閱:4下載:0
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • Abstract
    heMIMO-OFDMtechnologyandthemulti-modeQC-LDPCcodehavebeenappliedforthenewcommunicationsystemssuchasIEEE802.16eandIEEE802.11ntoachieveabetterperformanceinthewirelessdataaccess.Combiningwiththemulti-modeQC-LDPCcodeinthechanneldecoderwiththeMIMOreceiver,thereceivingsignalqualityisimprovedevenatthehighspeedmobilechannel.ButtheMIMOsymboldetectionisnoteasyforimple-mentationbecauseoftheoptimaldetectionmessagesearchingatthemulti-dimensionalchannelresponses.Intheotherway,themulti-modeQC-LDPCdecoderisso°exiblethatthegeneraldecodingarchitectureisnotsuitableforthisapplication.

    FortheMIMOsymboldetectorapplication,theK-bestspheredecodingestimatestheEuclideandistancesbetweenthereceivedsymbolsandexpectedconstellationmappingnodesusingthedecomposedchannelresponsesinfor-mation.TheswitchnetworkisimplementedtosortthesmallerEuclideandistanceforthesymbolvaluedecision.Themaximalsortingsizebecomeshuge,e.g.512.Asaresult,thetraditionalbutter°y-basedswitchnetworkcannotexecutethelargesizesorting.Wethereforeproposeaprogrammabledistortion-freeswitchnetworktoperformthelargesizesorting.Resultshowsthattheproposedswitchnetworkcanachievelesscomplexityinthehardwareimplementation.

    Inthemulti-modeQC-LDPCdecoder,thesub-matrixsizesaresovariable,andtheprogrammablemessagepassingnetwork(PMPN)isthekeycompo-nentforthe°exibledecoder.Basedonasinglebarrelshifterstructure,weproposethreecost-e®ectivePMPNsfortheIEEE802.16eandIEEE802.11nstandards.ThesignalroutingcongestionbetweenthePMPNsandthemem-orycanbereduced.Themulti-modeLDPCdecoderbasedontheproposedPMPNscanachieveahigherthroughputwithbetterhardwaree±ciency.


    摘要

    MIMO-OFDM的技術已經被大量應用在新的無線通訊系統規格中,例如IEEE802.16e與IEEE802.11n都採用了這項技術。使用多天線接收器的技術,可以大幅度改進接收器的性能,為了在移動的通道中獲取更佳的性能,目前在這兩種高速的通訊規格中,都採用多模的QC-LDPC做為通道解碼器,以搭配MIMO-OFDM信號偵測接收器。但在硬體實現方面,對於MIMO-OFDM的輸出速度,要求到非常高的吞吐率,而且會切換到不同的操作模式,因此實現MIMO的信號偵測或是多模的QC-LDPC解碼器,設計出高速且有彈性的架構都將會是一項很大的挑戰。

    在MIMO-OFDM的信號偵測的研究方向上,K-Best球型解碼器是目前較容易實現的演算法,此法會跟據QR分解後的多維度通道資訊,去計算收到的信號與預期對應的星座圖上節點的歐幾里得距離,並且使用網路交換器去搜尋出其中較小的歐幾里得距離所對應的節點,限制要搜尋的節點數目到K這樣的固定值,使得信號偵測實現的難度降低不少,具有將球型解碼器吞吐率固定的好處。但是在MIMO-OFDM中,這樣搜尋交換器的尺寸非常大,由其是要支援64-QAM高調變模式,在K的數值等於64的時後,有可能大到512這樣的尺寸,以至於傳統的butterfly-based的搜尋交換器很難被應用在這方面,在本文中,我們提出一種可程式化且無失真的搜尋交換器(programmable distortion-free switch network),採用新開發的搜尋演算法,希望用較小的硬體代價去實現這樣大尺寸的搜尋電路。

    在多模QC-LDPC通道解碼器方面,重點是如何設計出足夠彈性的電路去執行多種尺寸的解碼訊息交換,因為QC-LDPC規律的解碼矩陣特性,其矩陣是由位移後的對角矩陣與零矩陣組成,因此在內部子矩陣內的訊息交換,可以不採用複雜的cross-bar 網路交換器,僅使用一般的barrel位移器即可完成,我們提出三種基於單一尺寸的barrel位移器電路結構設計的可程式化訊息交換器(programmable message passing network),來搭配具有彈性的LDPC解碼器架構,以實現多種尺寸的訊息交換,這樣的電路已經被實現在IEEE802.16e與IEEE802.11n 的QC-LDPC解碼器晶片中,可同時支援此兩種規格,共22種不同的訊息尺寸,並且操作在較高的頻率,以增加整體解碼器的吞吐率,也解決因為支援多種尺寸訊息交換而造成的訊號繞線擁擠問題,使得晶片的後段設計與收斂更為容易,這樣的可程式化的訊息交換器架構可用最少的硬體成本去執行高速交換QC-LDPC 解碼器的資訊。

    Abstract Table of Contents List of Figures List of Tables 1 Introduction 1.1 Advances in Wireless Communications 1.2 Thesis Organization 2 Programmable Distortion-free Switch Network for K-best Sphere Decoder 2.1 K-best Sphere Decoding Algorithm 2.2 Programmable 192 £ 64 Distortion-free Switch Network 2.2.1 The Maximal Partial Euclidean Distance Filter Algorithm 2.2.2 The Programmable Distortion-free Switch Network Architecture 2.3 Implementation Result 3 LDPC Code Decoding Algorithm and Implementation 3.1 LDPC code 3.2 Min-sum algorithm 3.3 Implementation Approaches 4 Programmable Message Passing Networks for Multi-mode LDPC decoder 4.1 LDPC code applied for IEEE 802.16e/IEEE 802.11n 23 4.1.1 QC-LDPC H Matrix Structure in IEEE 802.16e/IEEE 802.11n 4.1.2 QC-LDPC Codes Parameter IEEE 802.16e/IEEE 802.11n 4.2 Programmable Message Passing Network 4.2.1 PMPN Routing Algorithm 4.2.2 Self-Routing Network 4.2.3 Shift-Routing Network 4.2.4 M-way Duplicated Network 4.3 PMPN-Based QC-LDPC Decoder Architecture 4.3.1 Node Processing Cel 4.4 Implementation Result 5 Conclusion 5.1 Summary 5.2 Future Work

    [1] Part 16: Air Interface for Fixed and Mobile Broadband Wireless Access Systems Amendment for Physical and Medium," IEEE P802.16e-2005, October 2005.
    [2] `IEEE 802.11 Wireless LANs WWiSE Proposal: High Throughput extension to the 802.11 Standard," IEEE 11-04-0886-00-000n.
    [3] R. Gallager, Low-density Parity-check Codes,"IEEE Trans. on Info. Theory,vol. 8, pp. 21-28, Jan. 1962.
    [4] J. L. Fan, Constrained Coding and Soft Iterative Decoding," Kluwer Academic Publishers, 2001.
    [5] J. Chen and M. Fossorier, Near Optimum Universal Belief Propagation Based Decoding of Lower-density Parity Check Codes,"IEEE Trans. on Communication, vol. 50, pp. 406-414, Mar. 2002.
    [6] D. MacKay and R. Neal, Near shannon limit performance of low density parity check codes," Electronics Letters, vol. 32, pp.1645-1646, Aug. 1996.
    [7] M. P. C. Fossorier, Quasi-cyclic Low-density Parity-check Codes from Circulant Permutation Matrices," IEEE Trans. on Info. Theory, vol. 50, pp.1788-1793, Aug. 2004.
    [8] L. Yang, H. Liu and C. J. R. Shi, Code construction and FPGA implementation of a low-error-foor multi-ratelow-density -check code decoder," IEEE Trans. on Circuits and Systems I, vol.53, issue 4, no. 5, pp. 892-904, Apri.
    2006.
    [9] C. P. Fewer, M. F. Flanagan and A. D. Fagan, Versatile Variable Rate LDPC Codec Architecture," IEEE Trans. on Circuits and Systems I, vol.54, no. 10, pp. 2240-2251, Oct. 2007.
    [10] A. Paulraj, R. Nabar, and D. Gore, Introduction to Space-Time Wireless Communications,"New York: Cambridge Univ. Press, 2003.
    [11] M. M. Mansour and N. R. Shanbhag, A 640-Mb/s 2048-Bit Programmable LDPC Decoder Chip," IEEE J. of Solid-State Circuits, vol. 41, no. 3, pp.634-698, Mar. 2006.
    [12] J. Tang, T. Bhatt, V. Sundaramurthy, and K. K. Parhi, Reconfigurable Shuffe Network Design in LDPC Decoders," Proc. of 17th International Conference on Application-specific Systems and Processors, pp.81-86, Sep. 2006.
    [13] X. Y. Shih, C. Z. Zhan, C. H. Lin, and A. Y. Wu, A 19-mode 8.29mm 52mW LDPC Decoder Chip for IEEE 802.16e System," IEEE J. of Solid-State Circuits, vol. 43, no. 3, pp.672-683, Mar. 2008.
    [14] S. H. Kang and I. C. Park, Loosely Coupled Memory-Base Decoding Architecture for Low Density Parity Check Codes," IEEE Trans. on Circuits and Systems I, vol. 53, no. 5, pp. 1045-1056, May 2006.
    [15] A. J. Blanksby and C. J. Howland, A 690mW 1Gb/s 1024b Rate 1/2 Low Density Parity Check Code Decoder," IEEE J. of Solid-State Circuits, vol.37, no. 3, pp. 404-412, Mar. 2002.
    [16] L. Chen, J. Xu, I. Djurdjevic and S. Lin, Near-Shannon-Limit Quasi-Cyclic Low-Density Parity-Check Codes," IEEE Trans. on Communications, vol. 52, pp. 1038-1042, Jul. 2004.
    [17] C. H. Liu, S. W. Yen, C. L. Chen, H. C. Chang, C. Y. Lee, Y. S.Hsu, and S. J. Jou, An LDPC Decoder Chip Based on Self-Routing Network for IEEE 802.16e Applications," IEEE J. of Solid-State Circuits, vol. 41, no. 3, pp.684-
    694, Mar. 2008.52
    [18] C. H. Liu, C. C. Lin , H. C. Chang , C. Y. Lee, and Y. S. Hsu, Multi-mode Message Passing Switch Networks Applied for QC-LDPC Decoder," IEEE Int.Symp. Circuits and Ssystems. (ISCAS), pp.752-755, May. 2008.
    [19] C. H. Liu, C. C. Lin, S. W. Yen, C. L. Chen, H. C. Chang, C. Y. Lee, Y.S.Hsu, and S. J. Jou, Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network (SRN)," IEEE Trans. on Circuits and Systems II, vol.
    56, no. 9, pp.734-738, Sep. 2009.
    [20] T. Brack, M. Alles, F. Kienle, and N. When, A Synthesizable IP Core for WiMAX 802.16E LDPC Code Decoding," IEEE 17th Interantional Symposium on Personal, Indoor and Mobile Radio Communications, pp.1-5. Sep.
    2006.
    [21] D. E. Hocevar, A Reduced Complexity Decoder Architecture via Layered Decoding of LDPC Codes," Proc. IEEE Workshop on Signal Processing Systems,pp. 107-112, Oct. 2004.
    [22] M. Karkooti, P. Radosavljevic, and J. R. Cavallaro, Configurable, High Throughput, Irregular LDPC Decoder Architecture: TradeoR Analysis and Implementation," Proc. of 17th International Conference on Application
    specific Systems and Processors, 2006.
    [23] M. Rovini, G. Gentile, and L. Fanucci, Multi-size Circular Shifting Networksfor Decoders of Structured LDPC Codes," Electronics Letters, vol. 43, issue 17, pp. 938-940, Aug. 2007.
    [24] A. J. Blanksby and C. J. Howland, A 690mW 1Gb/s 1024b Rate 1/2 Low Density Parity Check Code Decoder," IEEE J. of Solid-State Circuits, vol.37, no. 3, pp. 404-412, Mar. 2002.
    [25] J. Lin, Z.Wang, L. Li, J. Sha and M. Gao, Efficient Shu2e Network Architecture and Application for WiMAX LDPC Decoders" EEE Trans. on Circuitsand Systems II: Express Briefs, vol. 56, pp.215-219, March 2009.
    [26] C. C. Lin, K. L. Lin, H. C. Chang, and C. Y. Lee, A 3.33Gb/s (1200,720)low-density parity check code decoder," Proc. 31st Eur. Solid State Circuits Conf. (ESSCIRC), pp. 211V214. Sept. 2005,
    [27] T. Brack, M. Alles, F. Kienle, and N. When, A Synthesizable IP Core forWiMAX 802.16E LDPC Code Decoding," IEEE 17th Interantional Symposium on Personal, Indoor and Mobile Radio Communications, 2006.
    [28] D. E. Hocevar, A Reduced Complexity Decoder Architecture via Layered Decoding of LDPC Codes," Proc. IEEE Workshop on Signal Processing Systems,pp. 107-112, Oct. 2004.
    [29] M. Rovini, G. Gentile, and L. Fanucci, Multi-size Circular Shifting Networks for Decoders of Structured LDPC Codes," Electronics Letters, vol. 43, issue
    17, pp. 938-940, Aug. 2007.
    [30] D. oh and Keshab K. P. , Low-Complexity Switch Network for Reconfigurable LDPC Decoders ," IEEE Trans. on Very Large Scale Integer. (VLSI) Systm,pp.665-668, May. 2009.
    [31] D. Oh and K. K. Parhi, Area efficient controller design of barrel shifter for reconfigurable LDPC decoders," IEEE Int. Symp. Circuits and Systems. (ISCAS), pp.240V243, May 2008.
    [32] Z. Guo and P. Nilsson, Algorithm and implementation of the K-best sphere decoding for MIMO detection," IEEE J. of Selected Area in Communications,vol.24, no.3. pp.491-503, Mar. 2006.
    [33] M. Wenk, M. Zellweger at al., K-Best MIMO detection VLSI architectures achieving up to 424 Mbps," IEEE Int. Symp. Circuits and Ssystems. (ISCAS), pp.1151-1154, Sept. 2006.
    [34] Q. Li and Z. Wang, An Improved K-Best Sphere Decoding Architecture for MIMO Systems,"IEEE Signals, Systems and Computers. (ACSSC), pp. 2190-2194, Oct. 2006.
    [35] Shariat-Yazdi R. and Kwasniewski T., Programmable K-best MIMO Detector Architecture," IEEE Communications, Control and Signal Processing. (ISCCSP), issue 12-14, pp. 1565-1569, Mar. 2008.
    [36] C. H. Yang, and Markovic, D. A Multi-Core Sphere Decoder VLSI Architecture for MIMO for MIMO Communications," IEEE Global Telecommunications. (GLOBECOM), pp. 1-6, ,Dec. 2008.
    [37] H. L. Lin, R. C. Change and H. L. Chen, A High-Speed SDM-MIMO Decoder Using Efficient Candidate Sorting for Wireless Communication," IEEE Trans. on Circuits and Systems II, vol. 55, no. 3, pp. 289-293, March 2008.
    [38] Garrett, D. Knagge G. Davis, L. and Chris Nicol, 28.8 Mb/s 4X4 MIMO 3G CDMA Receiver for Frequency Selective Channels," IEEE J. of Solid-State Circuits, vol.40, no. 1, pp.320V330, Sept. 2005.
    [39] Garrett, D. Davis, L. Brink, S. Hochwald B. and Knagge G., Silicon complexity for maxima likelihood MIMO detection using spherical decoding," IEEE J. of Solid-State Circuits, vol.39, no. 9, pp.1544V1552, Sept. 2004.
    [40] A. Burg, M. Borgmann, M. Wenk, M.Zellweger, W.Fichtner and H.Bolcskei,VLSI Implementation of MIMO Detection Using the Sphere Decoding Algorithm," IEEE J. of Solid-State Circuits, vol. 40, no. 7, pp.1566-1577, July.
    2005.
    [41] Se-Hyeon K. and In-Cheol P. , High Speed Sphere Decoding Based on Vertically Incremental Computation ," IEEE Int. Symp. Circuits and Systems.(ISCAS), pp.665-668, May. 2007.
    [42] H. B.olcskei, D. Gesbert, C. Papadias, and A. J. van der Veen, Eds., Space Time Wireless Systems: From Array Processing to MIMO Communications,"Cambridge Univ. Press, 2006.
    [43] S. Chen, T. Zhang and Y. Xin, Relaxed K-Best MIMO Signal Detector Design and VLSI Implementation," IEEE Trans. on Very Large Scale Integer. (VLSI)
    Systm, pp. 328-337, vol.15, no.3, Mar. 2007.
    [44] S. Chen and T. Zhang, Low power soft-output signal detector design for wireless MIMO communication systems," International Symp. Low Power Electronics and Design, pp. 232-237, Aug. 2007.
    [45] Mahdi S. and P. Gleen G., A 0.13um CMOS 655Mbps 4x4 64-QAM MIMO detector," IEEE Int. Solid State Circuits Conf. (ISSCC), pp.256-258, 2009

    無法下載圖示 全文公開日期 本全文未授權公開 (校內網路)
    全文公開日期 本全文未授權公開 (校外網路)

    QR CODE