針對時脈閘控與工程變更設計之有效率的關鍵時序分析與函數彈性勘查

簡易檢索 / 詳目顯示

回結果列表

研究生：	郭育旻 Kuo, Yu-Min
論文名稱：	針對時脈閘控與工程變更設計之有效率的關鍵時序分析與函數彈性勘查 Efficient Timing Criticality Analysis and Functional Flexibility Exploration for Clock Gating and ECO Designs
指導教授：	張世杰 Chang, Shih-Chieh
口試委員:
學位類別：	博士 Doctor
系所名稱：	電機資訊學院 - 資訊工程學系 Computer Science
論文出版年：	2009
畢業學年度：	97
語文別：	英文
論文頁數：	117
中文關鍵詞：	時序分析、電源閘控、時脈閘控、工程變更
外文關鍵詞：	Timing analysis, Power gating, Clock gating, Engineering change
相關次數：	點閱：3 下載：0
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

在這篇論文中，我們研究要達到成功電路時序優化所需要的二個重要主題。第一個主題是快速且準確的時序分析，而第二個主題是函數彈性的探索以便達到設計的時序優化和功能更正。首先，在先進的超大型積體電路設計流程中，準確的時序分析為電路優化之主要關鍵，要改進時序分析引擎的運行時間，我們首先提出時間布林特徵函數，它是一個非常高效率的表示方法尤其是應用在時間自動測試向量產生和電路延遲計算。基於這個有效率的分析工具，然後我們提出一個針對電源閘控設計的時序分析方法，並考慮去耦電容的插入及隨著時間變化的電壓下降問題。另外，為了改進電路的時序，我們從電路中訊號的相關性來得到函數彈性。使用時脈閘控的彈性，我們針對循序電路提出反覆優化技術使時序改善。使用將電路邏輯的輸入端連接到電源端或接地端的彈性，我們針對工程變更問題提出一個反覆方法得到可實作的電路分解。

In this thesis, we explore two essential topics required for a successful circuit timing optimization. The first topic is a fast but accurate timing analysis while the second topic is the functional flexibility so as to achieve timing optimization and functional correction of a design. First of all, the accurate timing is extremely crucial in the advanced VLSI design process for the circuit optimization. To improve the run time of a timing analysis engine, we first present a very efficient formula of timed Boolean characteristic functions for timed automatic test pattern generation and circuit delay computation. With this very efficient analysis tool, we then present a timing analysis approach for power gating designs considering the decoupling capacitance insertion and the time-varying IR drop issue. In addition, to improve the timing of a circuit, we propose to optimize the circuit by utilizing the flexibility from functional correlations. Using the flexibility of the clock gating, we propose an iterative optimization technique to minimize the overall timing for a sequential circuit. Using the flexibility of tying inputs to Vdd or Gnd, we propose an iterative method to generate feasible mapping solutions for the EC problem.

Chapter 1 Introduction    6
Chapter 2 Efficient Boolean Characteristic Function for Timed Automatic Test Pattern Generation    9
1    Introduction    9
2    Timed Characteristic Function    14
3    Efficient TCF Implementation    19
3.1    Recursive TCF Formulations    19
3.2    Sharing Mechanism for TCFs    25
3.3    Correlation Information Extraction    28
4    Overall Algorithm Flow    30
5    Experimental Results    32
5.1    Results of the Efficient TCF Construction    32
5.2    Results of the Circuit Delay Computation    35
6    Summary    41
Chapter 3 Timing Analysis Considering IR Drop Waveforms in Power Gating Designs    42
1    Introduction    42
2    Fast IR Drop Estimation    45
2.1    Basic Architecture of a Power Gating Design    45
2.2    IR Drop Waveform Estimation without Decaps    48
2.3    IR Drop Waveform Estimation with Decaps    50
2.4    IR Drop Waveform Estimation with Decaps Considering Vector Correlation    53
3    Timing Analysis with IR Drop Waveforms    55
4    Experimental Results    58
5    Summary    61
Chapter 4 A Novel Sequential Circuit Optimization with Clock Gating Logic    62
1    Introduction    62
2    Logic Synthesis Using the Clock Gating Function    68
2.1    Basic definitions and key facts    68
2.2    Simplest implementations of FNS and FCG    70
2.3    Heuristic minimization for FNS and FCG    72
3    Experimental Results    78
4    Summary    81
Chapter 5 Spare Cells with Constant Insertion for Engineering Change    82
1    Introduction    82
2    Mapping with Spare Cells    87
2.1    Problem of Mapping with Quantity Constraint    87
2.2    Quantity Constraint Checking with Constant Insertion    91
2.3    Iterative Mapping Solution Generation    95
3    Overall Flow    99
4    Experimental Results    100
5    Summary    103
Chapter 6 Conclusion    105
References    107

                                

[1] P. Ashar, and S. Malik, “Functional Timing analysis Using ATPG,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, no. 8, pp. 1025-1030, Aug. 1995.
[2] R. I. Bahar, H. Cho, G. D. Hachtel, E. Macii, and F. Somenzi, “Timing analysis of Combinational Circuits using ADD’s,” in Proc. IEEE European Design Test Conference, pp. 625-629, 1994.
[3] H. C. Chen, and D. Du, “Path Sensitization in Critical Path Problem,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 2, pp. 196-207, Feb. 1993.
[4] S. Devadas, K. Keutzer, and S. Malik, “Computation of Floating Mode Delay in Combinational Circuits: Theory and Algorithms,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 12, pp. 1913-1923, Dec. 1993.
[5] N. Een, and N. Sörensson, “A SAT Solver with Conflict-Clause Minimization,” SAT 2005. [Online]. Available: http://minisat.se/MiniSat.html.
[6] J. L. Güntzel, A. C. M. Pinto, and R. Reis, “A Timed Calculus for ATG-Based Timing analysis of Circuits with Complex Gates,” in Proc. IEEE Latin American Test Workshop, pp. 234-239, 2001.
[7] H. Kriplani, F. Najm, and I. N. Hajj, “Pattern Independent Maximum Current Estimation in Power and Ground Buses of CMOS VLSI Circuits: Algorithms, Signal Correlations, and Their Resolution,” IEEE Trans. on Computer-Aided Design, vol. 14, no. 8, pp. 998-1012, Aug. 1995.
[8] Y. M. Jiang, A. Krstic, and K. T. Cheng, “Estimation for Maximum Instantaneous Current Through Supply Lines for CMOS Circuits,” IEEE Trans. on Very Large Scale Integration Systems, vol. 8, no. 1, pp. 61-73, Feb. 2000.
[9] Y. M. Jiang, K. T. Cheng, and A. Krstic, “Estimation of Maximum Power and Instantaneous Current Using a Genetic Algorithm,” in Proc. IEEE Custom Integrated Circuits Conference, pp. 135-138, 1997.
[10] R. Kundu, and R. D. Blanton, “Timed Test Generation for Crosstalk Switch Failure in Domino CMOS Circuits,” in Proc. IEEE VLSI Test Symposium, pp. 379-385, 2002.
[11] R. Kundu, and R. D. Blanton, “ATPG for Noise-Induced Switch Failures in Domino Logic,” in Proc. International Conference on Computer-Aided Design, pp. 765-768, 2003.
[12] P. C. McGeer, A. Saldanha, P. R. Stephan, R. K. Brayton, and A. L. Sangiovanni-Vicentelli, “Timing analysis and Delay-Fault Test Generation using Path-Recursive Functions,” in Proc. International Conference on Computer-Aided Design, pp. 180-183, 1991.
[13] P. C. McGeer, and R. K. Brayton, Integrating Functional and Temporal Domains in Logic Design, Kluwer Academic Publishers, 1991.
[14] M. W. Moskewicz, C. F. Madigan, Y. Zhao, L. Zhang, and S. Malik, “Chaff: Engineering an efficient SAT solver,” in Proc. Design Automation Conference, pp. 530-535, 2001.
[15] J. P. M. Silva, and K. A. Sakallah, “Efficient and Robust Test Generation-Based Timing analysis,” in Proc. International Symposium on Circuits and Systems, pp. 303-306, 1994.
[16] J. P. M. Silva, and K. A. Sakallah, “GRASP: A Search Algorithm for Propositional Satisfiability,” IEEE Trans. on Computers, vol. 48, no. 5, pp. 506-521, May 1999.
[17] L. G. Silva, J. P. M. Silva, L. M. Silveira, and K. A. Sakallah, ”Satisfiability Models and Algorithms for Circuit Delay Computation,” ACM Trans. on Design Automation of Electronic Systems, vol. 7, no. 1, pp. 137-158, Jan. 2002.
[18] H. Yalcin, and J. P. Hayes, “Hierarchical Timing analysis Using Conditional Delays,” in Proc. International Conference on Computer-Aided Design, pp. 371-377, 1995.
[19] H. Zhang, “SATO: An Efficient Propositional Prover,” in Proc. International Conference on Automated Deduction, pp. 272-275, 1997.
[20] M. K. Michael, T. Haniotakis, and S. Tragoudas, “A Unified Framework for Generating All Propagation Functions for Logic Errors and Events,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pp. 980-987, vol. 23, no. 6, June 2004.
[21] S. Padmanaban and S. Tragoudas, “Efficient Identification of (Critical) Testable Path Delay Faults Using Decision Diagrams,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 1, pp. 77-87, January 2005.
[22] K. Yang, K. T Cheng, and L. C Wang, “TranGen: A SAT-Based ATPG for Path-Oriented Transition Faults,” in Proc. Asian and South Pacific Design Automation Conference, pp. 92-97, 2004.
[23] Y. M. Kuo, Y. L. Chang, and S. C. Chang, “Efficient Boolean Characteristic Function for Fast Timed ATPG,” in Proc. International Conference on Computer-Aided Design, pp. 96-99, 2006.
[24] W. K. C. Lam, and R. K. Brayton, Timed Boolean Functions: A Unified Formalism for Exact Timing Analysis, Kluwer Academic Publishers, 1994.
[25] S. Devadas, A. Ghosh, and K. Keutzer, Logic Synthesis, McGraw-Hill, Inc. 1994.
[26] S. Roy, P. P. Chakrabarti, and P. Dasgupta, “Event Propagation for Accurate Circuit Delay Calculation Using SAT,” ACM Trans. on Design Automation Electronic Systems, vol. 12, no. 3. Article 36, August 2007.
[27] T. Larrabee, “Test Pattern Generation Using Boolean Satisfiability,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 11, no. 1, Jan. 1992.
[28] R. Ahmadi and F. N. Najm, “Timing Analysis in Presence of Power Supply and Ground Voltage Variations,” Proc. of ICCAD, pp. 176-183, 2003.
[29] M. Anis, S. Areibi, and M. Elmasry, “Dynamic and Leakage Power Reduction in MTCMOS Circuits Using an Automated Efficient Gate Clustering Technique,” Proc. of DAC, pp. 480-485, 2002.
[30] G. Bai, S. Bobba, and I. N. Hajj, “Static Timing Analysis Including Power Supply Noise Effect on Propagation Delay in VLSI Circuits,” Proc. of DAC, pp. 259-300, 2001.
[31] P. Chen, Y. Kukimoto, and K. Keutzer, “Refining Switching Window by Time Slots for Crosstalk Noise Calculation,” Proc. of ICCAD, pp. 583-586, 2002.
[32] M. Hashimoto, J. Yamaguchi, and H. Onodera, “Timing Analysis Considering Spatial Power/Ground Level Variation,” Proc. of ICCAD, pp. 814-820, 2004.
[33] C. T. Hsieh, J. C. Lin, and S. C. Chang, “A Vectorless Estimation of Maximum Instantaneous Current for Sequential Circuit,” Proc. of ICCAD, pp. 537-540, 2004.
[34] H. Jiang, M. Marek-Sadowska, and S. R. Nassif, “Benefits and Costs of Power-Gating Technique,” Proc. of ICCD, pp. 559-566, 2005.
[35] Y. M. Jiang, K. T. Cheng, and A. Krstic, “Estimation of Maximum Power and Instantaneous Current using a Genetic Algorithm,” Proc. of CICC, pp. 135-138, 1997.
[36] H. Kriplani, F. N. Najm, and I. N. Hajj, “Pattern Independent Maximum Current Estimation in Power and Ground Buses of CMOS VLSI Circuits: Algorithms, Signal Correlations, and Their Resolution,” IEEE Trans. on CAD, Vol. 14, No. 8, pp. 998-1012, Aug. 1995.
[37] A. Krstic and K. T. Cheng, “Vector Generation for Maximum Instantaneous Current through Supply Lines for CMOS Circuits,” Proc. of DAC, pp. 383-388, 1997.
[38] A. Krstic, Y. M. Jiang, and K. T. Cheng, “Pattern Generation for Delay Testing and Dynamic Timing Analysis Considering Power-Supply Noise Effects,” IEEE Trans. on CAD, Vol. 20, No. 3, pp. 416-425, Mar. 2001.
[39] C. Long and L. He, “Distributed Sleep Transistor Network for Power Reduction,” IEEE Trans. on VLSI, Vol. 12, No. 9, pp. 937-946, Sep. 2004.
[40] S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada , “1-v Power Supply High-speed Digital Circuit Technology with Multithreshold-voltage CMOS,” IEEE J. Solid-State Circuits, pp. 847-854, Aug. 1995.
[41] S. Pant and D. Blaauw, “Static Timing Analysis Considering Power Supply Variations,” Proc. of ICCAD, pp. 365-371, 2005.
[42] K. Tseng and M. Horowitz, “False Coupling Exploration in Timing Analysis,” IEEE Trans. on CAD, Vol. 24, No. 11, pp. 1795-1805, Nov. 2005.
[43] D. S. Chiou, D. C. Juan, Y. T. Chen, and S. C. Chang, “Fine-Grained Sleep Transistor Sizing Algorithm for Leakage Power Minimization,” Proc. of DAC, pp. 81-86, 2007.
[44] D. S. Chiou, S. H. Chen, S. C. Chang and C. W. Yeh, “Timing Driven Power Gating,” Proc. of DAC, pp. 121-124, 2006.
[45] P. Babighian, L. Benini, and E. Macii, “A Scalable Algorithm for RTL Insertion of Gated Clocks Based on ODCs Computation,” IEEE Trans. on CAD, vol. 24, no. 1, Jan 2005.
[46] M. Alidina, J. Monteiro, S. Devadas, and A. Ghosh, “Precomputation-Based Sequential Logic Optimization for Low Power,” Proc. of ICCAD, pp. 74-81, 1994.
[47] L. Benini, and G. De Micheli, “Automatic Synthesis of Low-Power Gated-Clock Finite-State Machines,” IEEE Trans. on CAD, vol. 15, no. 6, Jun. 1996.
[48] M. Müch, B. Wurth, R. Mehra, J. Sproch, and N. When, “Automating RT-Level Operand Isolation to Minimize Power Consumption in Datapaths,” Proc. of DATE, pp. 624-633, 2000.
[49] V. Tiwari, S. Malik, and P. Ashar, “Guarded Evaluation: Pushing Power Management to Logic Synthesis/Design,” Proc. of ISPLED, pp. 221-226, 1995.
[50] H. Kapadia, L. Benini, and G. De Micheli, “Reducing Switching Activity on Datapath Buses with Control-Signal Gating,” IEEE J. of Solid-State Circuits, vol. 34, no. 3, March 1999.
[51] M. Onishi, A. Yamada, H. Noda, and T. Kambe, “A Method of Redundant Clocking Detection and Power Reduction at RT Level Design,” Proc. of ISLPED, pp. 131-136, 1997.
[52] L. Benini, G. De Micheli, E. Macii, M. Poncino, and R. Scarsi, “Symbolic Synthesis of Clock-Gating Logic for Power Optimization of Synchronous Controllers,” ACM Trans. on Design Automation Electronic Systems, vol. 4, no. 4, pp. 351-375, 1999.
[53] G. Lakshminarayana, A. Raghunathan, K. S. Khouri, N. K. Jha, and S. Dey, “Common-Case Computation: A High-Level Technique for Power and Performance Optimization,” Proc. of DAC, pp 56-61, 1999.
[54] Y. Luo, J. Yu, J. Yang, and L. Bhuyan, “Low Power Network Processor Design Using Clock Gating,” Proc. of DAC, pp. 13-17, 2005.
[55] H. M. Jacobson, “Improved Clock-Gating through Transparent Pipelining,” Proc. of ISLPED, pp. 26-31, 2004.
[56] N. Banerjee, K. Roy, H. Mahmoodi, and S. Bhunia, “Low Power Synthesis of Dynamic Logic Circuits Using Fine-Grained Clock Gating,” Proc. of DATE, pp. 6-10, 2006.
[57] A. P. Hurst, “Automatic Synthesis of Clock Gating Logic with Controlled Netlist Perturbation,” Proc. of DAC, pp. 654-657, 2008.
[58] D. Brand, A. Drumm, S. Kundu, and P. Narain, “Incremental Synthesis,” in Proceedings of the International Conference on Computer-Aided Design, pp. 14-18, Nov. 1994.
[59] T. H. Cormen, C. E. Leiserson, and R. L. Rivest, Introduction to Algorithms, MIT Press, 2000.
[60] G. De Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994.
[61] N. Eén and N. Sörensson, “Translating Pseudo-Boolean Constraints into SAT,” Journal on Satisfiability, Boolean Modeling and Computation, vol. 2, pp. 1-26, Mar. 2006.
[62] S. Y. Huang, K. C. Chen, and K. T. Cheng, “AutoFix: A Hybrid Tool for Automatic Logic Rectification,” IEEE Transactions on Computer-Aided Design of Integrated its and Systems, vol. 18, no. 9, pp. 1376-1384, Sep. 1999.
[63] F. Koushanfar, J. L. Wong, J. Feng, and M. Potkonjak, “ILP-Based Engineering Change,” in Proceedings of the Design Automation Conference, pp. 910-915, June 2002.
[64] C. C. Lin, K. C. Chen, and M. Marek-Sadowska, “Logic Synthesis for Engineering Change,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 3, pp. 282-292, Mar. 1999.
[65] C. H. Lin, Y. C. Huang, S. C. Chang, and W. B Jone, “Design and Design Automation of Rectification Logic for Engineering Change,” in Proceedings of the Asia and South Pacific Design Automation Conference, pp. 1006-1009, Jan. 2005.
[66] T. Shinsha, T. Kubo, Y. Sakataya, J. Koshishita, and K. Ishihara, “Incremental Logic Synthesis Through Gate Logic Structure Identification,” in Proceedings of the Design Automation Conference, pp. 391-397, June 1986.
[67] G. Swamy, S. Rajamani, C. Lennard, and R. K. Brayton, “Minimal Logic Re-Synthesis for Engineering Change,” in Proceedings of the International Symposium on Circuits and Systems, pp. 1596-1599, June 1997.
[68] Y. Wantanabe and R. K. Brayton, “Incremental Synthesis for Engineering Changes,” in Proceedings of the International Conference on Computer Design, pp. 40-43, Oct. 1991.
[69] Y. M. Kuo, Y. T. Chang, S. C. Chang, and M. Marek-Sadowska, “Engineering Change Using Spare Cells with Constant Insertion,” in Proceedings of the International Conference on Computer Aided Design, pp. 544-547, 2007.
[70] Y. P. Chen, J. W. Fang, and Y. W. Chang, “ECO Timing Optimization Using Spare Cells,” in Proceedings of the International Conference on Computer Aided Design, pp. 530-535, 2007.
[71] For details of the flows, the physical design considerations, and additional experimental results, please refer to the website. [Online]. Available: http://cid-495b33b6ba3a659b.skydrive.live.com/self.aspx/EC/appendix.pdf.

全文公開日期本全文未授權公開 (校內網路)
全文公開日期本全文未授權公開 (校外網路)

簡易檢索 / 詳目顯示

相關論文