本論文包含兩個主題，第一個主題是三維立體堆疊晶片邏輯運算單元及緩衝器;第二個主題是高速無記憶體之數位頻率合成器。
運用三維製程技術設計邏輯運算單元，改編Zhuang full adder為了減少關鍵延遲時間而達到高速加法器實現在三維空間，成為一個全新的架構。本論文研究發現，現今的三維製程技術在設計電路上必須加入緩衝器才足夠驅動訊號在矽穿孔(TSV)中做傳遞，故研究兩種不同效能的緩衝器，可依照訊號需求或電路規格配置不同的緩衝器，分別有高速效能的Super buffer可驅動高速操作頻率，以及低消耗功率的低振幅訊號緩衝器，可在傳遞低頻訊號時節省消耗功率，此主題共分成四個測試晶片分別有Super buffer輸入輸出延遲時間為109 ps、低振幅訊號緩衝器消耗功率為5.7 μW、4-bit Zhuang carry-select adder使用Super buffer做TSV傳遞輸入輸出延遲時間為230 ps和4-bit Zhuang carry-select adder使用低振幅訊號緩衝器做TSV傳遞最大操作頻率為1 GHz。
有高解析度及寬頻的高速頻率合成器在現今的無線傳輸系統中是很重要的需求，而傳統無ROM(Read Only Menory)的數位式頻率合成器用到了弦波函數合成器以數位碼去產生近似的弦波，但弦波函數合成器大量的運用到運算邏輯單元(ALU)而增加速度上的限制，而本研究目的是以低複雜度的弦波合成技術來實現高速數位式頻率合成器，其中利用到非線性Sine-Weighted 的Current-Steering DAC以及高速的Sparse-2 Ling adder來設計4 GHz 7-bit 無記憶體數位式頻率合成器。

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