中 文 摘 要

我們已經研究金屬-高介電係數介電層-高介電係數介電層-氧化物-矽結構(MHHOS-type flash memory) 使用Ta2O5 作為電荷儲存層、Y2O3、ZrO2、La2O3作為阻擋氧化層結構的電容器和電晶體。為了作為比較，我們也製作了用SiO2作為阻擋氧化層的元件(MOHOS-type flash memory)。並對各種結構的元件作基本的電性量測與可靠度分析。我們針對不同的結構，對其電容器與電晶體做了各種電性上的討論。
我們也探討了MOTOS結構電容的漏電流傳導機制。穿遂氧化層中，我們預期是Direct tunneling或是Fowler-Nordheim tunneling主導。電荷儲存層中，我們在電場小於0.3 MV/cm的情況之下，fit到Poole-Frenkel emission。在阻擋氧化層中，我們發現是由Schottky emission與Fowler-Nordheim tunneling主導。電場在0.5 MV/cm~1 MV/cm的情況下，由Schottky emission主導；電場大於1 MV/cm的情況下，變為由Fowler-Nordheim tunneling主導。
在MYTOS和MLTOS電容器方面，兩者的C-V memory window分別為1.6V和2.52V。而此兩種結構的電容器電荷保持時間都有達到10年的水準。
在電晶體方面，記憶體特性也是MYTOS和MLTOS兩種電晶體表現最好。此兩種電晶體，在Vp=6V，pulse width為10ns的寫入狀態之下，Vth的變化量分別為1.5V和1.6V，皆已經達到我們定義的寫入標準。IDS-VGS memory window分別為1.6V和1.7V，在四種結構中表現是比較好的兩種。在電荷保持時間方面，也都能達到10年的水準。

Abstract
Conventional SONOS (polysilicon-oxide-nitride-oxide-silicon) non-volatile memory devices use silicon nitride as the charge storage layer. In this work, metal－high-k dielectric－high-k dielectric－oxide－silicon (MHHOS) capacitors and transistors were fabricated using Ta2O5 as the charge storage layer and Y2O3, La2O3 as the blocking oxide layers. Both Al/Y2O3/Ta2O5/SiO2/Si and Al/La2O3/Ta2O5/SiO2/Si capacitors achieve retention time longer than 10 years. In addition, the conduction mechanism under positive bias for Al/SiO2/Ta2O5/SiO2/Si capacitors was studied. With Ta2O5 as the charge storage layer, the dominating conduction mechanism at 495 K with the electric field lower than 0.3 MV/cm is Poole-Frenkel emission. With SiO2 as the blocking layer, the dominating conduction mechanism at the electric field of 0.5 MV/cm < E < 1 MV/cm and in the temperature range from 448 K to 495 K is Schottky emission. The dominating conduction mechanism with the electric field above 1 MV/cm and at the temperature lower than 58 K is Fowler-Nodheim tunneling.

The programming and erase times of the Al/Y2O3/Ta2O5/SiO2/Si and the Al/Y2O3/Ta2O5/SiO2/Si transistors are characterized. With a programming stress pulse voltage of 6 V, the threshold voltage shift of more than 0.5 V for both structures are achieved in 10 ns. With a erase stress pulse voltage of -8 V, the erase times of the Al/Y2O3/Ta2O5/SiO2/Si and Al/La2O3/Ta2O5/SiO2/Si transistors are 10μs and 1μs, respectively. The retention properties of MHHOS transistors were also characterized. The Al/Y2O3/Ta2O5/SiO2/Si transistor can keep a ΔVth window of 0.89 V for 10 years. The corresponding number for the Al/La2O3/Ta2O5/SiO2/Si transistor is 0.83 V for 10 years.

References

[1] D. Kahng and S. M. Sze, “A floating gate and its application to memory devices,” IEEE Trans. Electron Devices, vol. 14, no. 9, pp.629-629, 1967.
[2] D. Frohman-Bentchkowsky, “A fully decoded 2048-bit electrically programmable MOS-ROM,” IEEE ISSCC Dig. Tech. Papers, pp. 80-81, 1971.
[3] H. A. R. Wegener, A. J. Lincoln, H. C. Pao, M. R. O’Connell, and R.E. Oleksiak, “The variable threshold transistor, a new electrically alterable, non-destructive read-only storage device,” IEDM Tech. Dig., 1967.
[4] W. J. Tsai, N. K. Zous, C. J. Liu, C. C. Liu, C. H. Chen, T. Wang, S. Pan, C. Y. Lu, and S.H. Gu, “Data retention behavior of a SONOS type two-bit storage flash memory cell,” IEDM Tech. Dig., pp. 32.6.1 -32.6.4., 2001.
[5] T. Sugizaki, M. Kobayashi, M. Ishidao, H. Minakaca, M. Yamaguchi, Y. Tamura, Y. Sugiyama, T. Nakanishi, and H. Tanaka, “Novel multi-bit SONOS type flash memory using a high-K charge trapping layer,” IEEE Symp. VLSI Technology Digest of Technical, pp. 24-28, 2003.
[6] C. T. Swift, G. L. Chindalore, K. Harber, T. S. Harp, A. Hoefler, C. M. Hong, P. A. Ingersoll, C. B. Li, E. J. Prinz, and J. A. Yater, “An embedded 90nm SONOS nonvolatile memory utilizing hot electron programming and uniform tunnel erase,” IEDM Tech. Dig., pp. 927-930, 2002.
[7] S. Tiwari, F. Rana, H. Hanafi, A. Hartstein, E. F. Crabbe, and K. Chan, “A silicon nanocrystals based memory,” Appl. Phys. Lett., vol. 68, no. 10, pp. 1377-1379, 1996.
[8] Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal nanocrystal memories—Part I: Device design and fabrication,” IEEE Trans. Electron Devices, vol. 49, no. 9, pp. 1606-1613, 2002.
[9] Y. N. Tan, W. K. Chim, B. J. Cho, and W. K. Choi, ”Over-erase phenomenon in SONOS-type flash memory and its minimization using a hafnium oxide charge storage layer,” IEEE Trans. Electron Devices, vol. 51, no. 7, pp. 1143-1147, 2004.
[10] B. Jiankang and M. H. White, “Design considerations in scaled SONOS nonvolatile memory devices,” Solid-State Electron., vol. 45, pp. 113–120, 2001.
[11] H. Wann and C. Hu, “High endurance ultrathin tunnel oxide in MONOS device structure for dynamic memory applications,” IEEE Electron Device Lett., vol. 16, pp. 491–493, 1995.
[12] Y. Kamagaki, S. I. Minami, T. Hagiwara, K. Furusawa, T. Furuno, K. Uchida, M. Terasawa, and K. Yamazaki, “Yield and reliability of MNOS EEPROM products,” IEEE J. Solid-State Circuits, vol. 24, pp. 1714–1722, 1989.
[13] M. H. White, D. A. Adams, and B. Jiankang, “On the go with SONOS,” IEEE Circuits Devices Mag., vol. 16, pp. 22–31, 2000.
[14] W. D. Brown and J. E. Brewer, Eds., Nonvolatile semiconductor memory technology, a comprehensive guide to understanding and using NVSM devices. New York: IEEE Press, pp. 193–309, 1998.
[15] Yamada, Y. Hiwa, T. Tamane, K. Amemiya, Y. Ohshima, and K. Yoshikawa, ”Degradation mechanism of flash EEPROM program after program/erase cycles,” IEDM Tech. Dig., pp. 23-26, 1993.
[16] W. J. Tsai, N. K. Zous, C. J. Liu, C. C. Liu, C. H. Chen, T. Wang, S. Pan, C. Y. Lu, and S. H. Gu, ”Data retention behavior of a SONOS type two-bit storage flash memory cell”, IEDM Tech. Dig., pp. 719-722, 2001.
[17] B. Jiankangand and M. H. White, “Effects of two-step high temperature deuterium anneals on SONOS nonvolatile memory devices”, IEEE Electron Device Lett., vol. 22, no. 1, pp. 17 -19, 2001.
[18] S. M. Sze, Physics of Semiconductor Device, 2nd ed, Wiley, New York, 1981.
[19] J. R. Yeargan and H. L. Taylor, “The Poole-Frenkel effect with compensation present,” J. Appl. Phys. vol. 39, no. 12, pp. 5600-5604 , 1968.
[20] W. J. Zhu, T. P. Ma, T. Tamagawa, J. Kim, and Y. Di, “Current transport in metal/hafnium oxide/silicon structure,” IEEE Electron Device Lett., vol. 23, no. 2, pp. 97-99, 2002.
[21] D.K. Schroder, “Semiconductor material and device characteristics,” Wiley, Arizona, 1998.
[22] M. Lenzlinger and E. H. Snow, “Fowler-Nordheim tunneling into thermally grown SiO2,” J. Appl. Phys., vol. 40, no. 1, pp. 278-283, 1969.
[23] H. Bachhofer, H. Reisinger, E. Bertagnolli, H. von Philipsborn, “Transient conduction in multidielectric silicon–oxide–nitride–oxide semiconductor structures,” J. Appl. Phys. vol. 89, no. 5, pp. 2791-2800 , 2001.
[24] M. French, H. Sathianathan, and M. White, “A SONOS nonvolatile memory cell for semiconductor disk application,” IEEE Nonvolatile Memory Technology Review, pp. 70-73, 1993.
[25] M. S. Joo, B. J. Cho, C. C. Yeo, D. S. H. Chan, S. J. Whoang, S. Matthew, L. K. Bera, N. Bala, and D. L. Kwong, “Formation of hafnium-aluminum-oxide gate dielectric using single cocktail liquid source in MOCVD process,” IEEE Trans. Electron Devices, vol. 50, no. 10, pp. 2088-2094, 2003.
[26] S. Zafar, A. Callegari, E. Gusev, and M. V. Fischetti, “Charge trapping related threshold voltage instabilities in high permittivity gate dielectric stacks,” J. Appl. Phys., vol. 93, no. 11, pp. 9298-9300, 2003.
[27] X. Wang, J. Liu, W. Bai, D. L. Kwong, “A Novel MONOS-Type Nonvolatile Memory Using High-k Dielectrics for Improved Data and Programming Speed,” IEEE Trans. Electron Devices, vol. 51, no. 4, pp. 597-602, Apr. 2004.
[28] X. Wang, D. L. Kwong, “A Novel High-κ SONOS Memory Using TaN/Al2O3/Ta2O5/HfO2/Si Structure for Fast Speed and Long Retention Operation,” IEEE Trans. Electron Devices, vol. 53, no. 1, pp. 78-82, Jan. 2006.
[29] Y. N. Tan, W. K. Chim, W. K. Choi, M. S. Joo, and B. J. Cho, “Hafnium aluminum oxide as charge storage and blocking-oxide layer in SONOS-type nonvolatile memory for high-speed operation,” IEEE Trans. Electron Devices, vol. 53, no. 4, pp. 654-661, 2006.
[30] W. J. Tsai, N. K. Zous, C. J. Liu, C. C. Liu, C. H. Chen, T. Wang, S. Pan, C. Y. Lu, and S. H. Gu, “Data retention behavior of a SONOS type two-bit storage flash memory cell, ” IEDM Tech. Dig., pp. 719-722, 2001.