簡易檢索 / 詳目顯示

研究生: 陳揚哲
Chen, Yang-Che
論文名稱: 使用可程式化邏輯閘實現量子密鑰分發系統的硬體加速
Hardware Acceleration of the Quantum Key Distribution System using FPGA
指導教授: 馬席彬
Ma, Hsi-Pin
口試委員: 黃稚存
Huang, Chih-Tsun
褚志崧
Chuu, Chih-Sung
蔡佩芸
Tsai, Pei-Yun
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2025
畢業學年度: 113
語文別: 英文
論文頁數: 104
中文關鍵詞: 量子密鑰分發系統可程式化邏輯閘傳輸控制協定網際網路通訊協定篩選錯誤協調隱私放大身分驗證硬體實作
外文關鍵詞: QKD, TCP/IP, Sifting, Error Reconciliation, Hardware Implementation
相關次數: 點閱:58下載:0
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • 在近年來量子計算的發展下,傳統加密方法已被證實存在被破譯的風險。為了因應量子計算帶來的挑戰,量子密鑰分發(quantum key distribution, QKD)基於量子物理特性,提供一種全新的安全加密方法。 QKD 系統通過量子訊號進行加密,其中的後處理需要使用大量的計算和內存資源,並使用安全的古典通道進行訊息傳輸,最終生成安全的量子密鑰。
    該系統包括三個主要組成部分:量子位檢測協議(篩選)、錯誤更正和隱私放大。本論文中的系統通訊由一條古典通道完成,該通道利用網際網路協定第四版完成傳輸控制協定(TCP)並且以 1 G 乙太網實現。為了確保古典通道的安全性,系統將所有透過古典通道傳輸的訊息輸入雜湊模組(hashing module)以生成獨特的標籤進行驗證。
    本論文介紹了一種基於相干單向(coherent one-way, COW)協議的量子密鑰分發(QKD)系統,並實現於 AMD Kintex UltraScale+ FPGA KCU116 Evaluation Kit FPGA 板上。該系統在理論上可達到每秒 5.6 Mbps 的最大密鑰生成速率,並支持高達每秒 18.71 Mbps 的古典通道傳輸速率。此外,通過基於 FPGA 的實現,對實際吞吐量進行了評估。本研究證明了 FPGA 技術有效提升 QKD 系統性能和可靠性。


    In recent years, with the advancement of quantum computing, traditional en-cryption methods have been proven to be at risk of being compromised. To address the challenges posed by quantum computing, quantum key distribution (QKD) of-fers a new secure encryption method based on the principles of quantum physics. QKD system received quantum signals for encryption, the encryption required the authenticated channel to generate secure quantum keys.
    The QKD system comprises three main components: quantum bit detection agreement (sifting), error correction, and privacy amplification. In this thesis, the communication between these components is facilitated by a classical chan-nel that utilizes the transmission control protocol (TCP) over Internet protocol ver-sion 4 (IPv4). This channel operates with a 1 G small form-factor pluggable (SFP) transceiver. Acknowledgment mechanisms are integrated into the TCP framework to guarantee reliable data exchange, while a hashing module generates unique au-thentication tags to secure the classical channel.
    This thesis presents a quantum key distribution (QKD) system based on the coherent one-way (COW) protocol, implemented on the AMD Kintex UltraScale+ FPGA KCU116 Evaluation Kit. The system achieves a theoretical peak secret key generation rate of 5.6,Mbps and supports classical channel transmission rates of up to 18.71,Mbps. The practical throughput is also evaluated through an FPGA-based implementation. This work demonstrates the effectiveness of FPGA technology in enhancing the performance and reliability of QKD systems.

    摘要i 誌謝iii Abstract v 1 Introduction 1 1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Background Knowledge and Literature Survey 7 2.1 Quantum Key Distribution Cryptography . . . . . . . . . . . . . . . . . . . . 7 2.1.1 Sifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.2 Error Reconciliation . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1.3 Privacy Amplification . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1.4 Authentication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1.5 Key Size Decrease During Distillation . . . . . . . . . . . . . . . . . . 12 2.2 Classical Channel Network Protocol . . . . . . . . . . . . . . . . . . . . . . . 13 2.3 Related Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3 Implementation of FPGA-Based Secret Key Distillation System 21 3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2 Submodules Designated for Partially Integration . . . . . . . . . . . . . . . . . 31 3.2.1 Sifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.2.2 Error Reconciliation . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.2.3 Privacy Amplification . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.2.4 Packet and Unpacket . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.2.5 Classical Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.3 Implementation of Partially Integration . . . . . . . . . . . . . . . . . . . . . . 65 3.3.1 Data Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.3.2 Host Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.4 Submodules Allocated for Top-Level System Integration . . . . . . . . . . . . 66 3.4.1 Distillation Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.4.2 AXI BRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . 70 3.4.3 AXI Manager IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.5 Implementation of Top-Level System Integration . . . . . . . . . . . . . . . . 75 3.5.1 Data Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 3.5.2 Host Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 3.6 Authentication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4 Implementation and Evaluation Results 83 4.1 Utilization of Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 4.2 Classical Channel of Transmitting Path . . . . . . . . . . . . . . . . . . . . . . 84 4.3 Classical Channel of Receiving Path . . . . . . . . . . . . . . . . . . . . . . . 87 4.4 Summary of Delay in Classical Channel . . . . . . . . . . . . . . . . . . . . . 88 4.5 Processing Rate Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5 Conclusion and Future Works 99 5.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.2 Future Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 References 101

    [1] M. Sharma, V. Choudhary, R. Bhatia, S. Malik, A. Raina, and H. Khandelwal, “Leveraging
    the power of quantum computing for breaking rsa encryption,” Cyber-Physical Systems,
    vol. 7, pp. 1–20, 09 2020.
    [2] H.-K. Lo and H. F. Chau, “Unconditional Security of Quantum Key Distribution over
    Arbitrarily Long Distances,” Science, vol. 283, no. 5410, pp. 2050–2056, 1999.
    [3] V. Scarani, H. Bechmann-Pasquinucci, N. J. Cerf, M. Dušek, N. Lütkenhaus, and M. Peev,
    “The security of practical quantum key distribution,” Reviews of modern physics, vol. 81,
    no. 3, pp. 1301–1350, 2009.
    [4] P. W. Shor and J. Preskill, “Simple proof of security of the BB84 quantum key distribution
    protocol,” Physical review letters, vol. 85, no. 2, p. 441, 2000.
    [5] R. A. Qamar, M. A. Maarof, and S. Ibrahim, “First tour to quantum cryptography,” International
    Journal of Research and Reviews in Computer Science, vol. 2, no. 2, p. 326,
    2011.
    [6] Q. Li, S. Ma, H. Mao, and L. Meng, “An FPGA-based communication scheme of classical
    channel in high-speed QKD system,” in 2014 Tenth International Conference on Intelligent
    Information Hiding and Multimedia Signal Processing, pp. 227–230, IEEE, 2014.
    [7] J. Constantin, R. Houlmann, N. Preyss, N. Walenta, H. Zbinden, P. Junod, and A. Burg,
    “An FPGA-based 4 Mbps secret key distillation engine for quantum key distribution systems,”
    Journal of Signal Processing Systems, vol. 86, pp. 1–15, 2017.
    [8] N. Venkatachalam, F. P. Shingala, C. Selvagangai, S. Dillibabu, P. Chandravanshi, R. P.
    Singh, et al., “Scalable QKD post processing system with reconfigurable hardware accelerator,”
    IEEE Transactions on Quantum Engineering, 2023.
    [9] D. Stucki, N. Brunner, N. Gisin, V. Scarani, and H. Zbinden, “Fast and simple one-way
    quantum key distribution,” Applied Physics Letters, vol. 87, no. 19, 2005.
    [10] R.-Q. Gao, Y.-M. Xie, J. Gu, W.-B. Liu, C.-X. Weng, B.-H. Li, H.-L. Yin, and Z.-B. Chen,
    “Simple security proof of coherent-one-way quantum key distribution,” Optics Express,
    vol. 30, no. 13, pp. 23783–23795, 2022.
    [11] A. Tanaka, M. Fujiwara, K.-i. Yoshino, S. Takahashi, Y. Nambu, A. Tomita, S. Miki,
    T. Yamashita, Z. Wang, M. Sasaki, et al., “High-speed quantum key distribution system
    for 1-Mbps real-time key generation,” IEEE Journal of Quantum Electronics, vol. 48,
    no. 4, pp. 542–550, 2012.
    [12] Q. Li, Z. Lin, D. Le, and H. Liu, “An FPGA-based design of efficient QKD sifting module,”
    in 2014 Tenth International Conference on Intelligent Information Hiding and Multimedia
    Signal Processing, pp. 219–222, IEEE, 2014.
    [13] H.-F. Zhang, J. Wang, K. Cui, C.-L. Luo, S.-Z. Lin, L. Zhou, H. Liang, T.-Y. Chen,
    K. Chen, and J.-W. Pan, “A real-time QKD system based on FPGA,” Journal of Lightwave
    Technology, vol. 30, no. 20, pp. 3226–3234, 2012.
    [14] G. K. Shaw, S. Sridharan, and A. Prabhakar, “Optimal temporal filtering for cow-qkd,”
    in 2022 IEEE International Conference on Signal Processing and Communications (SPCOM),
    pp. 1–4, 2022.
    [15] J. Martinez-Mateo, C. Pacher, M. Peev, A. Ciurana, and V. Martin, “Demystifying the
    information reconciliation protocol cascade,” arXiv preprint arXiv:1407.3257, 2014.
    [16] H. Yan, T. Ren, X. Peng, X. Lin, W. Jiang, T. Liu, and H. Guo, “Information reconciliation
    protocol in quantum key distribution system,” in 2008 Fourth International Conference on
    Natural Computation, vol. 3, pp. 637–641, IEEE, 2008.
    [17] H. Krawczyk, “LFSR-based hashing and authentication,” in Annual International Cryptology
    Conference, pp. 129–139, Springer, 1994.
    [18] A. Tanaka, W. Maeda, S. Takahashi, A. Tajima, and A. Tomita, “Ensuring quality of shared
    keys through quantum key distribution for practical application,” IEEE Journal of Selected
    Topics in Quantum Electronics, vol. 15, no. 6, pp. 1622–1629, 2009.
    [19] L. E. Bassham III, A. L. Rukhin, J. Soto, J. R. Nechvatal, M. E. Smid, E. B. Barker, S. D.
    Leigh, M. Levenson, M. Vangel, D. L. Banks, et al., Sp 800-22 rev. 1a. a statistical test
    suite for random and pseudorandom number generators for cryptographic applications.
    National Institute of Standards & Technology, 2010.
    [20] K. R. Kurose, “Computer networking: A top-down approach, 7th edition,” Kurose, Keith
    W. Ross.—, p. 601, 2017.
    [21] N. Walenta, A. Burg, D. Caselunghe, J. Constantin, N. Gisin, O. Guinnard, R. Houlmann,
    P. Junod, B. Korzh, N. Kulesza, et al., “A fast and versatile quantum key distribution system
    with hardware key distillation and wavelength multiplexing,” New Journal of Physics,
    vol. 16, no. 1, p. 013047, 2014.
    [22] S.-S. Yang, Z.-L. Bai, X.-Y. Wang, and Y.-M. Li, “Fpga-based implementation of sizeadaptive
    privacy amplification in quantum key distribution,” IEEE Photonics Journal,
    vol. 9, no. 6, pp. 1–8, 2017.
    [23] S.-Y. Lai, “An FPGA-Based Secret Key Distillation Engine for Quantum Key Distribution
    System,” master’s thesis, National Tsing Hua University, Hsinchu, Taiwan, 2023.
    [24] Y.-F. Lu, “The Physical Channel Interface for Quantum Key Distribution Using FPGA,”
    master’s thesis, National Tsing Hua University, Hsinchu, Taiwan, 2023.
    [25] D. Stucki, N. Brunner, N. Gisin, V. Scarani, and H. Zbinden, “Fast and simple one-way
    quantum key distribution,” Applied Physics Letters, vol. 87, no. 19, 2005.
    [26] A. Stanco, F. B. Santagiustina, L. Calderaro, M. Avesani, T. Bertapelle, D. Dequal, G. Vallone,
    and P. Villoresi, “Versatile and concurrent FPGA-based architecture for practical quantum communication systems,” IEEE Transactions on Quantum Engineering, vol. 3,
    pp. 1–8, 2022.
    [27] E. O. Kiktenko, A. O. Malyshev, M. A. Gavreev, A. A. Bozhedarov, N. O. Pozhar, M. N.
    Anufriev, and A. K. Fedorov, “Lightweight authentication for quantum key distribution,”
    IEEE Transactions on Information Theory, vol. 66, no. 10, pp. 6354–6368, 2020.

    QR CODE