在單晶片系統的發展過程中，越來越多的嵌入式核心被整合在單一晶片中，也因此晶片的測試與診斷變成越來越重要的課題。在這篇論文中，我們提出了一個內建自我測試與診斷(BIST, BISD)的架構，此架構可以用以測試靜態隨機存取記憶體(SRAM)與內容定址記憶體(CAM)。藉由診斷電路我們能夠驗證我們的設計，也可以用以改善良率，此外，這個架構亦可支援平行處理與多埠(multi-port)的靜態隨機存取記憶體和內容定址記憶體，而且此架構只需小塊的晶片面積。
在這篇論文中，我們亦提出了一個用以排程待測記憶體的方法，並且將此方法實現在我們所設計的內建式自我診斷電路編譯器中，經由這個排程，我們可以縮短測試數個記憶體的測試時間。此外，我們提出另一個測試排程演算法，經由此演算法，我們可以保持測試時功率消耗穩定，即在每一個測試群組中，整體功率消耗大致相同。

為了要減低晶片在加入我們的內建式自動測試電路後所增加的繞線複雜度，並且同時縮減測試時間，這篇論文也提出的一個 Hamming syndrome 的壓縮方法，此方法主要是利用簡化後的赫夫曼編碼(Huffman Coding)，並且將每一個256位元的 Hamming syndrome 切割成數個固定長度的區塊，再逐一針對這些區塊編碼。根據模擬結果，對16位元的區塊而言，平均壓縮率可以減至9%左右。

整體來說，這篇論文主要是提出一個用於記憶體自我測試與診斷的架構，並且經由一些方法來縮小此架構的面積和測試時間，我們更推廣此架構支援單系統晶片中同時測試數個多埠記憶體，為了滿足設計自動化的考量，我們設計了一個編譯器用來自動產生這個自我診斷電路。

Testing and diagnosis are becoming important issues in system-on-chip (SoC) development while more and more embedded cores are integrated into single chips. We propose a built-in self-test and self-diagnosis scheme for embedded SRAMs and CAMs. It supports manufacturing test as well as diagnosis for design verification and yield improvement. With low hardware cost, our
memory BIST can handle various types of SRAM and CAM including pipeline and multi-port. In additional, a test scheduling methodology and a BIST compiler is also implemented, which aims

on reducing the testing time as well as test development time. To simplify the routing and reduce the test time of the proposed BISD circuit, a hamming syndrome compression scheme is also proposed. By using a simplified Huffman coding scheme and partitioning each 256-bit Hamming syndrome into fixed-size blocks. The average compression ratio is reduced to about 9% assuming 16-bit blocks.

[1] C.-F. Wu, C.-T. Huang, and C.-W. Wu, “RAMSES: a fast memory fault simulator,” in Proc.IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems (DFT), (Albuquerque), pp. 165–
173, Nov. 1999.
[2] K.-J. Lin and C.-W. Wu, “Testing content-addressable memories using functional fault mod-els
and March-like algorithms,” IEEE Trans. Computer-Aided Design, vol. 19, no. 5, pp. 577–588, May 2000.
[3] C.-F. Wu, C.-T. Huang, K.-L. Cheng, and C.-W. Wu, “Simulation-based test algorithm gen-eration
for random access memories,” in Proc. IEEE VLSI Test Symp. (VTS), (Montreal),pp. 291–296, Apr. 2000.
[4] C.-F. Wu, C.-T. Huang, C.-W. Wang, K.-L. Cheng, and C.-W. Wu, “Error catch and analysis for semiconductor memories using March tests,” in Proc. IEEE Int. Conf. Computer-Aided
Design (ICCAD), (San Jose), pp. 468–471, Nov. 2000.
[5] A. J. van de Goor, Testing Semiconductor Memories: Theory and Practice. Chichester, Eng-land:John Wiley & Sons, 1991.
[6] R. Dekker, F. Beenker, and L. Thijssen, “A realistic fault model and test algorithm for static random access memories,” IEEE Trans. Computer-Aided Design, vol. 9, no. 6, pp. 567–572,
June 1990.
[7] A. J. van de Goor and S. Hamdioui, “An experimental analysis of spot defects in srams:realistic fault models and tests,” in IEEE Asian Test Symp. (ATS), (Taipei), pp. 131–138,
2000.
[8] J.-F. Li, R.-S. Tzeng, and C.-W. Wu, “Using syndrome compression for memory built-in self-diagnosis,” in Proc. Int. Symp. VLSI Technology, Systems, and Applications (VLSI-TSA),
(Hsinchu), pp. 303–306, Apr. 2001.
[9] C. Cheng, C.-T. Huang, J.-R. Huang, C.-W. Wu, C.-J. Wey, and M.-C. Tsai, “BRAINS: A BIST complier for embedded memories,” in Proc. IEEE Int. Symp. Defect and Fault Toler-ance
in VLSI Systems (DFT), (Yamanashi), pp. 299–307, Oct. 2000.
[10] A. Benso, S. Di Carlo, G. Di Natale, P. Prinetto, and M. Lobetti-Bodorni, “A programmable BIST architecture for clusters of multiple-port SRAMs,” in Proc. Int. Test Conf. (ITC),pp. 557–566, 2000.
[11] R. D. Adams and E. S. Cooley, “Analysis of a deceptive destructive read memory fault model and recommanded testing,” in IEEE North Atlantic Test Wordshop, 1996.