具直流偏移校正與增益校準迴路之短通道可變增益放大器

簡易檢索 / 詳目顯示

回結果列表

研究生：	楊蕙甄 Yang, Hui-Chen
論文名稱：	具直流偏移校正與增益校準迴路之短通道可變增益放大器 A Short-Channel Variable Gain Amplifier with DC Offset Cancellation and Gain Calibration Loop
指導教授：	謝志成 Hsieh, Chih-Cheng
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2010
畢業學年度：	98
語文別：	英文
論文頁數：	92
中文關鍵詞：	短通道、可變增益放大器、省面積、增益校準、直流偏移校正
外文關鍵詞：	Short-channel, Variable Gain Amplifier, Area-saving, Gain Calibration, DC Offset Cancellation
相關次數：	點閱：2 下載：0
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

在本論文中，提出了一個具數位控制回授迴路的短通道可變增益放大器。為了節省面積，整體電路均使用最小通道長度的CMOS元件。此設計將導致電路產生嚴重的製程變異。為了解決這項問題，將需要兩個分別用來控制直流偏移校正以及增益校準的數位回授迴路。
此可變增益放大器採用具有衰減式電阻網路的全差動式增益級架構。藉由數位控制來改變電阻網路的阻值，以提供足夠的增益範圍與解析度。為了正確設定可變增益放大器的增益值，數位式的增益控制迴路必須在可變增益放大器操作之前啟動。直流偏移校正迴路則一直維持啟動狀態，用以防止輸出電壓飽和。藉由這兩個控制迴路，此可變增益放大器將不受製程變異的影響。
此量測晶片採用台積電0.18-μm 1P6M互補式金屬半導體氧化物製程，面積共佔292 μm × 592 μm。此可變增益放大器可提供-3.9 ~ 48.3 dB的增益範圍，在增益間距為6-dB的前提下，實際量測所得增益值和理想值之間的誤差值小於0.5 dB。在最大增益的設定下，頻寬為10.85 MHz。在輸出訊號為10-MHz，輸出擺幅為400-mVppd的情形下，總諧波失真 (THD) 在最大和最小的增益設定下分別為 -33.82 dB 和 -48.08 dB。當輸入的直流偏移電壓在-70 ~ +50 mV的範圍內時，輸出的偏移電壓小於20 mV。在1.8-V電壓供應的前提下，此晶片消耗12.1 mA的電流。

In this thesis, a short-channel variable gain amplifier with digital feedback loops is proposed. For the purpose of area saving, the entire work is implemented with minimum gate length CMOS devices. This results in severe circuit process variations. To overcome this problem, two digital feedback loops are needed for the DC offset cancellation and gain calibration.
The VGA circuit is based on a fully-differential gain stage with a degeneration resistor network. The resistance of this resistor network is digitally controlled to provide enough gain range and resolution. To properly set the VGA gain, the digital gain calibration loop is enabled before the VGA operates. The DC offset cancellation loop is always active to prevent the VGA output from DC saturation. With the aid of both loops, the proposed VGA is robust against process variations.
An experimental chip is fabricated in TSMC 0.18-μm 1P6M CMOS process. The core area occupies 292 μm × 592 μm. The available gain range of the VGA is -3.9 ~ 48.3 dB. For a 6-dB gain step requirement, the gain error is less than 0.5 dB. The bandwidth at the maximum gain setting is 10.85 MHz. With 10-MHz 400-mVppd sinusoidal output waveform, the total harmonic distortion (THD) at maximum and minimum gain setting are -33.82 dB and -48.08 dB respectively. The output DC offset voltage is less than 20 mV when the input DC offset voltage is within -70 ~ +50 mV. The current consumption from a single 1.8-V power supply is 12.1 mA.

List of Figures
List of Tables

Chapter 1: Introduction
1    Motivation
2    Receiver Architecture
3    Thesis Organization

Chapter 2: Architecture of the Short-Channel VGA
1  VGA Overview
1.1 VGA Fundamental
1.2 Linear-in-dB Gain Control
2  The Proposed Short-Channel VGA Architecture
2.1 VGA Gain Stages
2.2 DC Offset Cancellation Loop
2.3 Gain Calibtation Loop
3 Summary

Chapter 3: Design of the Short-Channel VGA Gain Stages
1  Overview
2  VGA Cell
3  MOS Resistor Network
4  Common Mode Feedback
5  Output Buffer
6  Bias Circuit
7  Simulation Results
8  Summary

Chapter 4: Design of the DC Offset Cancellation Loop
1  Overview
2  Operation of the DC Offset Cancellation Loop
2.1 Successive Approximation Register (SAR) Cancellation Path
2.2 Accumulator (ACC) Cancellation Path
3  Circuit Blocks
3.1 Comparator
3.2 Successive Approximation Register (SAR) Controller
3.3 Accumulator (ACC)
3.4 DAC
4  Simulation Results
5  Summary

Chapter 5: Design of the Gain Calibration Loop
1  Overview
2  Operation of the Gain Calibration Loop
3  Circuit Blocks
3.1 Fully-Differential S/H
3.2 Comparator
3.3 Successive Approximation Register (SAR) Controller
4  Simulation Results
5  Summary

Chapter 6: The Short-Channel VGA System Simulation and Measurement Results
1  Mixed-Mode Circuit Simulation
1.1 System Operation
1.2 Simulation Results
2  Chip Measurement
2.1 Measurement Setup
2.2 Measurement Results
3  Summary

Chapter 7: Conclusion and Future Works

Bibliography

                                

[1] J. Crols and M. Steyaert, "CMOS Wireless Transceiver Design", Kluwer Academic Publishers, 1997.
[2] B. Razavi, "Challenges in Portable RF Transceiver Design", IEEE Circuits and Devices Magazine, Vol. 12, pp. 12-25, Sept. 1996.
[3] John M. Khoury, "On the Design of Constant Settling Time AGC Circuit", IEEE Trans. Circuits Syst. II, Vol. 45, No. 3, Mar. 1998.
[4] Takafumi Yamaji, Nobuo Kanou and Tetsuro Itakura, "A Temperature-Stable CMOS Variable-Gain Amplifier with 80-dB Linearly Controlled Gain Range", IEEE Journal of Solid-State Circuits, Vol. 37, No. 5, May. 2002.
[5] Cheng-Chieh Chang and Shen-Iuan Liu, "Pseudo-Exponential Function for MOSFETs in Saturation", IEEE Trans. Circuits Syst. II, Vol. 47, No. 11, pp.1318-1321, Nov. 2000.
[6] J. J. F. Rijns, "CMOS Low-Distortion High-Frequency Variable-Gain Amplifier", IEEE Journal of Solid-State Circuits, Vol. 31, No. 7, Jul. 1996.
[7] Shoji Otaka, Gaku Takemura and Hiroshi Tanimoto, "A Low-Power Low-Noise Accurate Linear-in-dB Variable-Gain Amplifier with 500-MHz Bandwidth", IEEE Journal of Solid-State Circuits, Vol. 35, No. 12, Dec. 2000.
[8] Paolo Orsatti, Francesco Piazza and Qiuting Huang, "A 71-MHz CMOS IF-Baseband Strip for GSM ", IEEE Journal of Solid-State Circuits, Vol. 35, No. 1, Jan. 2000.
[9] K. M. Abdelfattah and A. M. Soliman, "Variable Gain Amplifiers Based on a New Approximation Method to Realize the Exponential Function", IEEE Trans. Circuits Syst. I, Vol. 49, No. 9, Sep. 2002.
[10] Y. Wang, B. Afshar, T.-Y. Cheng, V. Gaudet and Ali M. Niknejad, "A 2.5mW Inductorless Wideband VGA with Dual Feedback DC-Offset Correction in 90nm CMOS Technology", 2008 IEEE Radio Frequency Integrated Circuits Symposium.
[11] L. Sumanen, M. Waltari, and Kari Halonen, "A Mismatch Insensitive CMOS Dynamic Comparator for Pipeline A/D Converters", ICECS, Vol. 1, pp. 32-35, Dec. 2000.
[12] P. E.Allen and D. R. Holberg, "CMOS Analog Circuit Design", Chapter 9, Oxford University Press, 2002.
[13] Tzi-Hsiung Shu, Bang-Sup Song and Kantilal Bacrania, "A 13-b 10-Msample/s ADC Digitally Calibrated with Oversampling Delta-Sigma Converter", IEEE Journal of Solid-State Circuits, Vol. 30, No. 4, Apr. 1995.
[14] J.K. Kwon, K.D. Kim, W.C. Song and G.H. Cho, "Wideband high dynamic Range CMOS Variable Gain Amplifier for Low Voltage and Low Power Wireless Applications", Electron. Letter, Vol. 39, No. 10, pp. 759–760, Mar. 2003.
[15] Q.-H. Duong, L. Quan, and S.-G. Lee, "An All CMOS 84dB-Linear Low-Power Variable Gain Amplifier", IEEE Transactions on VLSI Circuits, pp. 114-117, Jun. 2005.
[16] Yun-Fan Chen, "A Linear-in-dB Variable Gain Amplifier with Background Digital DC Offset Cancellation Loop", National Tsing Hua University Master Thesis, 2007.
[17] H. Lee, K. Lee, S. Hong, "A Wideband CMOS Variable Gain Amplifier With an Exponential Gain Control", IEEE Trans. on Microwave Theory and Techniques, Vol. 55, No. 6, pp. 1363-1373, Jun. 2007.
[18] N. Ghittori, A. Vigna, P. Malcovati, S. D'Amico and A. Baschirotto, "Design of a Low-Power Variable Gain Amplifier for Reconfigurable Wireless Receivers", ICECS 2005.
[19] E. Brunner, "An ultra-low noise linear-in-dB variable gain amplifier for medical ultrasound applications", Proceedings of the WESCON'95, IEEE (1995), pp.650-655.

全文公開日期本全文未授權公開 (校內網路)
全文公開日期本全文未授權公開 (校外網路)

簡易檢索 / 詳目顯示

相關論文