The polysilicon-oxide-nitride-oxide-silicon (SONOS) flash memory has recently drawn noteworthy attention for applications in electrically erasable and programmable read-only memories (EEPROMs) due to the advantages of smaller cell size and better endurance characteristics for memory operation. Besides, the SONOS device is also one of the most promising candidates to realize the continuous vertical scaling on flash memory through the mechanism of charge trapping in its structure. However, programming/erasing speed, operating voltage and over-erasing are the main bottlenecks for SONOS devices in attempting to replace those floating-gate ones. Moreover, the phenomenon of electrons back tunneling (EBT) is known as a serious concern for NAND devices using Fowler-Nordheim (FN) operating due to the limitation of the low-erase states Vth during erasing. Many researches have been performed to overcome these limitations to replace the silicon nitiride. In this work, effects of the applications of stacked structure, high-k material and high work-function metal gate electrodes for charge trapping type flash devices were investigated.
For tunneling oxide, the application of multilayer dielectric stacks is promising to realize tunnel barrier engineering. With a suitable combination of stacked tunneling oxide (low-k/high-k), a lower operating voltage or higher programming speed can be achieved due to the engineered band diagrams. Furthermore, the high-k dielectric is considered for SiO2 replacement in sub-100 nm metal–oxide–semiconductor (MOS) technologies and represents a viable alternative for low-voltage, low-power sub-100-nm NVM nodes. Thus, the effects of stacked tunneling oxide on operating characteristics of charge trapping type flash devices were investigated.
For charge trapping layer, many researches have been performed by adopting various high-k materials to replace the silicon nitiride. Since the flash device with trapping layer of HfO2 has serious problem in retention characteristics and that with Al2O3 layer has the problem of low operation speed, flash device with HfAlO trapping layer seems to be a more feasible candidate because it is capable of possessing suitable charge-retention ability while keeping good over-erase resistance of HfO2 and reasonably fast operation speed. However, the optimal compositions in HfAlO charge trapping layer and the relevant physical mechanisms still remain unclear and thus are worth further exploring. In this work, operation performance of flash device with TaN/Al2O3/HfAlO/SiO2/Si (MAHOS) structure and various Al compositions in the HfAlO charge-trapping layer tuned by an atomic layer deposition (ALD) system were studied.
Besides, some literatures have reported the application of using band-gap engineering on the charge-trapping layer. Their results show enhancement on device operating and reliability performances, which present viable alternatives for low-voltage, low-power sub-100-nm NVM nodes. Among various potential options, the stacked high-k charge trapping layer in flash device has rarely been reported. Thus, effects of various single and stacked high-k trapping layers on the operating characteristics of charge trapping type flash devices are investigated and compared.
Finally, many researches have focused on high work function metal gate electrode due to the difficulties on satisfying NAND specifications and good retention characteristics. However, the integration of both high-WF metal gate and high-k trapping layer have rarely been reported. In this work, the effects of various metal gates and blocking oxide on operating characteristics of conventional SONOS devices were investigated. Then, the integration of MoN metal gate and HfAlO charge trapping layer were also studied. High speed operation and good reliability of charge-trapping type NVM were demonstrated.

隨著可攜式數位電子裝置產品之普及，非揮發性記憶體(NVM)因此有著極為蓬勃的發展。然而，當記憶體元件發展到次微米以下時，會面臨到操作速度與可靠度方面的瓶頸。在眾多替代方案中，SONOS結構因其結構發展成熟加上符合CMOS標準製程，因此成為具有高度潛力的取代方案。然而，隨著SONOS結構中的穿隧氧化層逐漸變薄，如何使該元件具有足夠的電荷保存力(data retention)將是SONOS需要面臨的問題。此外，在操作速度偏慢、操作電壓方面偏大及過度抹除(over-erase)等等的瓶頸，則是另外需要改善的課題。
首先，我們規劃了一系列採用堆疊式結構應用於charge trapping type flash元件之穿遂氧化層與電荷儲存層上的研究，預期將因此提升元件操作速度與電荷保存力等特性。我們先將堆疊式穿遂氧化層與電荷儲存層應用於傳統SONOS結構上，實驗結果可以觀察到當採用堆疊式結構取代傳統單一層tunneling oxide與trapping layer時，將可提昇元件的操作特性。
針對過度抹除與操作電壓方面等的瓶頸，我們將研究重心聚焦於電荷儲存層的變動。使用high-k材料(HfxAlyO)替換傳統Si3N4作為電荷儲存層，並針對此high-k材料中各元素之比例來做進一步的研究。實驗結果顯示，若以HfxAlyO作為電荷儲存層時，當元件之Hf/Al具有適當的比例下，將會得到較佳的快閃記憶體操作特性。接著進一步綜合以上兩者的研究結果，我們將堆疊結構搭配應用high-k trapping layer的charge trapping type元件上。首先利用調整Hf╱Al含量所形成的不同HfxAlyO材料，來調變材料能隙、缺陷數量與能階深淺等的物理特性。接著，再利用堆疊不同Hf╱Al含量之HfxAlyO層作為電荷儲存層的結構，以調整出具有最佳操作特性的電荷儲存層。
最後，由於之前研究之元件在抹除速度上仍有進一步改進的空間，因此我們另外規劃了一系列採用高功函數金屬閘極與高介電係數阻擋層於charge trapping type元件上的研究，預期會在抹除速度上帶來改進。首先，我們先將高功函數金屬MoN應用於傳統SONOS結構，實驗結果驗證了當高功函數金屬閘極被採用時，的確會改進抹除速度。因此，我們便繼續將此高功函數金屬搭配應用high-k電荷儲存層，並透過搭配高介電係數阻擋層來保持高功函數金屬之功函數值，而實驗的結果，也再次驗證了我們的預測。

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