現今消費者對電子產品之需求除朝向輕薄化、高效能及多功能外，大多數電子產品皆朝向可攜性發展，例如由桌上型電腦發展至筆記型電腦或是平板電腦，家用電話發展至手機甚至是多功能智慧型手機等。但這類可攜式電子產品常因運輸或使用時不慎摔落而遭致衝擊，造成內部構裝破壞或產品失效，因此如何增進可攜式電子產品之抗衝擊能力已成為先進構裝領域中之重要議題。
超細微間距多晶片模組(Ultra-Fine-Pitch Multi-Chip Module)不僅可整合多個晶片於單一構裝體，達到微型化目的，且因銲錫接點(Solder Joint)尺寸及間距大幅縮小，亦可有效降低電訊延遲(Signal Delay)及提升電信性能，故深受各界重視。為使業者有一可資評量及增進產品抗掉落衝擊能力之方法，本論文乃以超細微間距多晶片模組構裝為對象，並於JEDEC (Joint Electron Device Engineering Council)規範下，進行板層級(Board Level)掉落衝擊試驗。本論文應用有限單元套裝軟體ANSYS及LS-DYNA®進行數值模擬分析，對超細微間距多晶片模組之掉落衝擊可靠度進行探討，此外亦進行掉落衝擊試驗以驗證數值模擬結果。
掉落衝擊試驗主要在量測測試板(Test Board)之動態響應及超細微間距多晶片模組構裝之失效次數。在數值模擬分析中，本論文採用加速度輸入法(Input-G Method)來模擬測試板實際掉落之衝擊情形，並採用Johnson-Cook本構材料模型(Constitutive Model)，以考慮構裝材料之塑性及應變率效應。雖然JEDEC規範已明定試驗之實施方法、測試條件、測試載具規格及衝擊加速度容許誤差等細則，但對安裝測試板螺栓鬆緊度與測試條件容許誤差範圍大小對試驗結果之可能影響，並未見探討，故本論文亦對此二因子深入分析。
此外，本論文利用已驗證之有限單元數值分析模型進一步探討超細微間距多晶片模組之底膠(Underfill)塗佈、啞球(Dummy Bump)配置方式、微接點(Micro-Bump)偏移與溢錫及銲材厚度等因子對於微接點掉落衝擊可靠度之影響，以增進其抗衝擊能力。至於底膠塗佈、啞球配置、微接點型態以及容許誤差對超細微間距多晶片模組之掉落衝擊疲勞壽命預估，亦予評估。
本論文之成果將對提升超細微間距多晶片模組抗掉落衝擊能力，提供一可應用之設計方向。

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