降低製造的變異，提升良率是製造的目標，以往縮小製造變異的方法主要來自綿密的檢驗和統計製程管制，在製程或機台發生問題之前或問題之初期就能察覺，進行機台狀態維修或停機，讓問題不要繼續擴大。但進入奈米世代，許多製程對積體電路佈局的敏感度越來越顯著，製程的變異比例也隨著線寬的縮小而提高，許多與電路佈局設計相關的問題已經無法用傳統的檢驗和管制來解決，必須追本溯源到電路佈局設計來做改變與配合以提升其可製造性，這就是為何可製造性設計(Design for manufacturability)近來非常受到半導體產業界的重視。
化學機械研磨的平坦度和電路佈局(circuit layout)密度的均勻度有高度相關，虛擬電路填充在空曠區以增加整體佈局密度的均勻度證實是可行方法，且有許多填充最佳化的方法已經提出，但目前方法的目標函數對多功能的測試晶片(Combo-chips)並不適用，本研究提出以最小變異數法來最佳化多功能的測試晶片的佈局密度之均勻度以提升其可製造性。此外，毫秒快速高溫退火製程和電路佈局局部的吸收率息息相關，而局部的吸收率則和材質的組合相關，本研究提出針對毫秒高溫退火製程提出虛擬電路填充最佳化方法。
本研究分別探討化學機械研磨和毫秒高溫退火的虛擬電路填充最佳化，再以兩階段共同最佳化的方法探討化學機械研磨和毫秒高溫退火的虛擬電路填充的共同最佳化以及流程的整合。從實例驗證的結果發現本研究所提出之虛擬電路填最佳化之方法能有效提升佈局密度均勻度與表面吸收率的均勻度以提昇佈局設計在化學機械研磨和毫秒高溫退火製程的可製造性。

中文部分
王建榮 (2000)，半導體平坦化CMP技術，全華科技圖書股份有限公司。
王興毅 (2000)，IC製造業特性，工研院經資中心ITIS計畫。
莊達人 (1997)，VLSI製造技術，高立圖書有限公司。
羅正忠、張鼎張 (2003)，半導體製程技術導論，台灣培生教育出版股份有限公司。
張本法，結合類神經網路與基因演算法於下水聲源訊號辨識系統之研究, 中原大學碩士論文，民國89年7月。
張振松，資訊管理展望 第7 卷 第2 期 民國九十四年十月。
周慶華，整合基因演算法與類神經網路於現貨開盤指數之預測-以新加坡交易所摩根台股指數期貨為例, 輔仁大學碩士論文, 民國90年7月。
黃俊龍，應用基因演算法建立電子裝配業之資源配置決策模式, 東海大學碩士論文, 民國90年6月。
蔡明義，http://icmems.me.ncut.edu.tw/database/homepage/20100106化學機械拋光.pdf，民國99年1月。
英文部分
Ahsan, I. (2006). RTA-driven Intra-die Variations in Stage Delay and Parametric Sensitivities for 65nm Technology. VLSI symposium on Technology, 170-171

Autin, S. (1990). An introduction to genetic algorithms. AI Expert, 49-53.

Baker, K.R. (1971). Two process models in economic design of an X chart. AIIE Transactions, 3, 257-263.

Bielmann, M., Mahajan, U. and Singh, R. K. (1999). Effect of Particle Size during Tungsten Chemical Mechanical Polishing. Electrochemical and Solid State Letters, 2(8), 401-403.

Boning, D.S., Balakrishnan, K., Hong C., Drego, N., Farahanchi, A., Gettings, K.M., Lim D., Somani, A., Taylor, H., Truque, D. and Xie X. (2008). Variation. IEEE Transactions on Semiconductor Manufacturing, 21(1), 63-71.

Chang, K. J. (2004). Accurate on-chip variation modeling to achieve design for manufacturability. IEEE International Workshop on System-on-Chip for Real-Time Applications, 219-222.

Chang, K. J., Chou J. J., Li H. C. and Chang K. C. (2008). Impact quantification of the dummy metal fills on nanometer VLSI designs for DFM. IEEE International Symposium on VLSI Design, Automation and Test, 291-294.

Chang, R. and Spanos, C.J. (2005). Dishing-radius model of copper CMP dishing effects. IEEE Transactions on Semiconductor Manufacturing, 18(2), 297-303.

Chen, J. F., Staud, W. and Arnold, B. (2006). DFM Challenges for 32nm Node with Double Dipole Lithography (DDL) and Double Patterning Technology (DPT). IEEE International Symposium on Semiconductor Manufacturing, 479-482.

Chen, Y., Kahng, A. B., Robins, G. and Zelikovsky, A. (2002). Area Fill Synthesis for Uniform Layout Density. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 21(10), 1132-1147.

Chen, Y., Kahng, A.B., Robins, G. and Zelikovsky, A. (2002b). Monte Carlo Methods for Chemical–Mechanical Planarization on Multi-layer and Dual-material Models. Proceedings of SPIE, 4692, 421-432.

Cheng, Y. (2008). Design For Manufacturing (DFM) in Nano-CMOS era. IEEE International Nanoelectronics Conference, 524-529.

Chiang, C. and Kawa, J. (2006). Three DFM Challenges: Random Defects, Thickness Variation, and Printability Variation. IEEE Asia Pacific Conference on Circuits and Systems, 1099-1102.

Chien, C.F. and Hsu, C.Y. (2006). A novel method for determining machine subgroups and backups with an empirical study for semiconductor manufacturing. Journal of Intelligent Manufacturing, 17, 429-439.

Colin, A., Morin, P., Cacho, F., Bono, H., Beneyton, R., Bidaud, M., Mathiot, D. and Fogarassy, E. (2008). Simulation of the Sub-melt Laser Anneal Process in 45 CMOS Technology-Application to the Thermal Pattern Effects. Material Science and Engineering: B, 154-155, 31-34.

Cook, L.M. (1990). Chemical Process in Glass Polishing. Journal of Non-Crystalline Solids, 120, 152-171.

Davis, L. (1991). Handbook of Genetic Algorithms. Van Nostrand Reinhold, New York.

Debnath, G. and Thadikaran, P. (2009). Design for Manufacturability and Reliability in Nano Era. International Conference on VLSI Design, 33-34.

Divecha, R., Stine, B. E., Ouma, D. O., Yoon, J. U., Boning, D. S., Chung, J. E., Nakagawa, O. S. and Oh, S. Y. (1998). Effect of fine-line density and pitch on interconnect ILD thickness variation in oxide CMP process. 1997 Chemical Mechanical Polish for ULSI Multilevel Interconnection Conference, 7.

Doong, K.Y.Y., Lin, K.C., Tseng, T.C., Lu, Y.C., Lin, S.C., Hung, L.J., Ho, P.S., Hsieh, S., Young, K.L. and Liang, M.S. (2004). Electrical characterization of model-based dummy feature insertion in Cu interconnects. Proceedings of International Conference on Microelectronic Test Structures, 87-92.

Doong, K. Y. Y., Huang, C. H., Chu, C. C., Lin, S. C., Hung, L. J., Ho, P. S., Hsieh, S., Wang, C. J., Lin C. C. and Yang, K. L. (2004). Infrastructure development and integration of electrical-based dimensional process window checking. IEEE Transactions on Semiconductor Manufacturing, 17, 123-141.

Doong, K. Y. Y., Bordelon, T. J., Hung, L. J., Liao, C. C., Lin, S. C., Ho, P. S., Hsieh, S. and Yang, K. L. (2008). Field-Configurable Test Structure Array (FC-TSA): Enabling Design for Monitor, Model, and Manufacturability. IEEE Transactions on Semiconductor Manufacturing, 21, 169-179, 2008

Elakkumanan, P. (2008). Tutorial 6: Enhancing Yield through Design for Manufacturability (DFM). 9th International Symposium on Quality Electronic Design, 8-9.

Elbel, N., Neureither, B. and Ebersberger, B. (1998). Tungsten Chemical Mechanical Polishing. Journal of the Electrochemical Society, 145(5), 1659-1664

Faminan, J.M. (2009). A fitness-based weighting mechanism for multiciteria flowshop scheduling using genetic algorithm. International Journal of Advanced Manufacturing Technology, 43, 939-948.

Feng, L.M., Wang, Y. and Markle D.A. (2006). Minimizing Pattern Dependency in Millisecond Annealing. International Workshop on Junction Technology, 25-30.

Forschungszentrum Dresden-Rossendorf (2009). Flash Lamp Annealing. Available from: http://www.fzd.de/db/Cms?pOid=24140&pNid=0
[Accessed 11 Oct 2009]

Gennari, F. (2004). Optical Proximity Correction(OPC). Available from:
http://www.cs.berkeley.edu/~ejr/GSI/cs267-s04/homework-0/results/gennari/
[Accessed 07 Jun 2009]

Goldberg, D.E. (1989). Genetic Algorithms in Search, optimization and Machine Learning. Addison-Wesley.

Guo, Z.X., Wong, W.K., Leung, S.Y.S., Fan, J.T. and Chan, S.F. (2008). A genetic-algorithm-based optimization model for scheduling flexible assembly lines. International Journal of Advanced Manufacturing Technology, 36, 156-168.

Holland, John H (1975). Adaptation in Natural and Artificial Systems, University of Michigan Press, Ann Arbor.

Hongbo, S., Li, S., Degang, G. and Peng, L. (2006). Genetic simulated annealing algorithm-based assembly sequence planning. International Technology and Innovation Conference, 1573-1579.

Hung, W.L., Xie, Y., Vijaykrishnan, N., Addo-Quaye, C., Theocharides, T. and Irwin, M.J. (2005). Thermal-Aware Floorplanning Using Genetic Algorithms. International Symposium on Quality of Electronic Design, 634- 639.

ITRS (2007). International Technology Roadmap for Semiconductors 2007 Edition [online]. International Technology Roadmap for Semiconductors. Available from: http://www.itrs.net/Links/2007ITRS/2007_Chapters/2007_Interconnect.pdf
[Accessed 03 August 2008]

James, D. (2009). Design-for-manufacturing features in nanometer logic processes – a reverse engineering perspective. IEEE Custom Integrated Circuits Conference, 13-16.

Kahng, A.B., Robins, G., Singh, A., and Zelikovsky, A. (1999). Filling Algorithms and Analyzes for Layout Density Control. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 18 (4), 445–462.

Kahng, A.B. and Samadi, K. (2008). CMP Fill Synthesis: A Survey of Recent Studies. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 27 (1), 3-19.

Kathleen, A. P. (1998). Chemical Mechanical Polishing: The Impact of a New Technology on an Industry. Symposium on VLSI Technology Digest of Technical Papers, 2-5.

Kimuraa, Y. and Ida, K. (2006). Improved genetic algorithm for VLSI floorplan design with non-slicing structure. Computers and Industrial Engineering, 50(4), 528-540.

Kiyama, H., Kato, S., Aoyama, T., Onizawa, T., Ikeda, K., Kondo, H., Hashimoto, K., Murakawa, H. and Kuroiwa, T. (2010). Advanced Flash Lamp Annealing technology for 22nm and further device. 2010 International Workshop on Junction Technology (IWJT), 1-6.

Krishna, K., Ganeshan, K., and Ram, D.J. (1995). Distributed simulated annealing algorithms for job shop scheduling. IEEE Transactions on Systems, Man and Cybernetics, 25(7), 1102-1109.

Kubo, T., Sukegawa, T., Takii, E., Yamamoto, T., Satoh, S. and Kase, M. (2007). First Quantitative Observation of Local Temperature Fluctuation in Millisecond Annealing. IEEE International Conference on Advanced Thermal Processing of Semiconductors, 321-326.

Kubo, T., Sukegawa, T. and Kase, M. (2008). Total Temperature Fluctuation of a Patterned Wafer in the Millisecond Annealing. IEEE International Conference on Advanced Thermal Processing of Semiconductors, 195-199.

Kuhn, K., Kenyon, C., Kornfeld, A., Liu, M., Maheshwari, A., Shih, W.K., Sivakumar, S., Taylor, G., VanderVoorn and Samadi, K. (2008). Managing Process Variation in Intel’s 45nm CMOS Technology. Intel Technology Journal, 12 (2), 93-110.

Leonard, J. B. (2002). Mathematical modeling of polish rate decay in chemical- mechanical polishing. Journal of Engineering Mathematics, 43, 105-114.

Li, T.S., Huang, C.L. and Wu, Z.Y. (2006). Data Mining using genetic programming for construction of a semiconductor manufacturing yield rate prediction system. Journal of Intelligent Manufacturing, 17, 355-361.

Liu, C.W., Tsai, C.S, Liu J. M. and Shih, T. (2000). Method of Planarization using Dummy Leads. US Patent 6156660.

Mathworks (2009). Genetic algorithm and direct search toolbox 2 user’s guide.
http://www.mathworks.com/access/helpdesk/help/pdf_doc/gads/gads_tb.pdf. Accessed 6 October, 2009.

McMahon, R.A., Smith, R.A., Seffen, K.A., Voelskow, M., Anwand, W. and Skorupa, W. (2007). Flash-lamp annealing of semiconductor materials—applications and process models. Vacuum, 81, 1301-1305.

Michalewicz, Z. (1992). Genetic algorithms+data structures=evolution programs. Springer-Verlag, New York.

Nag, P. K., Maly, W and Jocobs, H. J. (1997). Simulation of Yield/Cost Learning Curves with Y4. IEEE Transaction on Semiconductor Manufacturing, 10(2), 256-266.

Nelson, M.M. (2003). Optimized pattern fill process for improve CMP uniformity and interconnect capacitance. Proceedings of the 15th Biennial, 374-375.

Nguyen, V. H., Velden, P.V.D., Daamen, D., Kranenburg, V. H. and Woerlee, P. H. (2000). Modeling of dishing for metal chemical mechanical polishing. International Electron Devices Meeting, 499-502.

Nishinohara, K.T., Ito, T. and Suguro, K. (2004). Improvement of performance deviation and productivity of MOSFETs with gate length below 30 nm by flash lamp annealing. IEEE Transactions on Semiconductor Manufacturing, 17(3), 286-291.

Ohta, T. and Suzuki, K. (2002). A new SP simultaneous polishing model for copper CMP process. International Conference on Simulation of Semiconductor Processes and Devices, 257-260.

Ouma, D.O., Boning, D.S., Chung, J.E., Easter, W.G., Saxena, V., Misra, S. and Crevasse, A. (2002). Characterization and Modeling of Oxide Chemical-Mechanical Polishing Using Planarization Length and Pattern Density Concepts. IEEE Transactions on Semiconductor Manufacturing, 15 (2), 232-244.

Park, T., Tugbawa, T., Boning, D., Chung, J., Hymes, S., Muralidhar, R., Wilks, B., Smekalin, K., and Bersuker, G. (1999). Electrical Characterization of Copper Chemical Mechanical Polishing. Chemical Mechanical Polish for ULSI Multilevel Interconnection Conference, 184-191.

Quirk, M., and Serda, J. (2001). Semiconductor Manufacturing Technology. Prentice Hall, Upper Saddle River, NJ.

Radojcic, R., Perry, D. and Nakamoto, M. (2009). Design for manufacturability for ables manufactuers. IEEE Solid-State Circuits Magazine, 1(3), 24-33.

Raghvendra, S. and Hurat, P. (2005). DFM: linking design and manufacturing. 18th International Conference on VLSI Design, 705-708.

Rao, R., Agarwal, K., Devgan, A., Nowka, K., Sylvester, D. and Brown, R. (2005). Parametric yield analysis and constrained-based supply voltage optimization. Sixth International Symposium on Quality of Electronic Design, 284-290.

Riviere-Cazaux, L., Lucas, K. and Fitch, J. (2005). Integration of design for manufacturability (DFM) practices in design flows. Sixth International Symposium on Quality of Electronic Design, 102-106.

Rung, R.D. 1981. Determining IC layout rule for cost minimization. IEEE Journal of Solid-State Circuits, 16(1), 35-42.

Runzi, C. and Yu, C. (2004). Modeling the electrical effects of metal dishing due to CMP for on-chip interconnect optimization. IEEE Transactions on Electron Devices, 51(10), 1577-1583.

Saraswat, K. and Shallow Junctions. Available from:
http://www.stanford.edu/class/ee311/NOTES/ShallowJunctions.pdf
[Accessed 05 Dec. 2009]

Scgnelli, D., Grant, C., Carrig, K., Kemerer T.-t., Landis, H., McDevitt, T., Sucharitaves, J., Tsai, E., Kumar, M. and Pastel, P. (2007). Pattern Density Methodology Using IBM Foundry Technologies. Electronic Components and Technology Conference, 1300-1307.

Sivanandam, S.N. and Deepa, S.N. 2008. Introduction to Genetic Algorithms. Springer, Berlin.

Srivastava, A., Shah, S., Agarwal, K., Sylvester, D., Blaauw, D. and Director, S. (2005). Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance. Design Automation Conference, 535-540.

Stavreva, Z., Zeidler, D., Plotner, M., Grasshoff, G. and Drescher, K. (1997). Chemical Mechanical Polishing of Copper for Interconnect Formation. Microelectronic Engineering, 33, 249-257.

Stine, B.E., Boning, D.S., Chung, J.E., Camilletti, L., Kruppa, F., Equi, E.R., Loh, W., Prasad, S., Muthukrishnan, M., Towery, D., Berman, M. and Kapoor, A. (1998). The physical and electrical effects of metal-fill patterning practices for oxide chemical-mechanical polishing processes. IEEE Transactions on Electron Devices, 45(3), 665-679.

Su, Y. H., Guo R. S. and Chang, H. H. (2006). Evolutionary Engineering Collaboration for DFM/DFY Solutions between Foundry and EDA Tool Vendor. IEEE International Symposium on Semiconductor Manufacturing, 475-478.

Tian, R., Wong, D., and Boone, R. (2001). Model-based Dummy Feature Placement for Oxide Chemical–Mechanical Polishing Manufacturability. IEEE Transaction on Computer-Aided Design, 20 (7), 902–910.

Tomozawa, M. (1997). Oxide CMP mechanisms. Solid-State Technology, 169-175.

Waltz, R.A. and Nocedal, J. (2006). KNITRO User's Manual. Optimization Technology Center, Northwestern University. Available from:
http://www.ece.northwestern.edu/~rwaltz/knitro/knitroman50.pdf
[Accessed 21 July 2008]

Wang, W. S. and Orshansky, M. (2006). Robust Estimation of Parametric Yield under Limited Descriptions of Uncertainty. IEEE/ACM International Conference on Computer-Aided Design, 884-890.

Wang, X., Chiang, C. C., Kawa, J. and Su, Q. (2005). A Min-Variance Iterative Method for Fast Smart Dummy Feature Density Assignment in Chemical-Mechanical Polishing. IEEE Sixth International Symposium on Quality Electronic Design (ISQED'05) , 258-263.

Wgsimon, Moore’s Law, Available from: http://en.wikipedia.org/wiki/Moore%27s_law. [Accessed Aug. 2008]

Ye, Y., Liu, F., Chen, M. and Cao, Y. (2009). Variability Analysis under Layout Pattern-Dependent Rapid-Thermal Annealing Process. Design Automation Conference, 551-556.

Yeric, G., Cohen, E., Garcia, J., Davis, K., Salem, E. and Green, G. (2005). Infrastructure for successful BEOL yield ramp, transfer to manufacturing, and DFM characterization at 65 nm and below. IEEE Design & Test of Computers, 22(3), 232-239.

Yu, T., Cheda, S., Ko, J., Roberton, M., Dengi, A. and Travis, E. (1999). A Two Dimensional Low Pass Filter Model for Die-level Topography Variation Resulting from Chemical Mechanical Polishing of ILD Films. International Electron Devices Meeting, 909-912.

Xiao, H. (2001). Introduction to Semiconductor Manufacturing Technology. Prentice Hall.

Zhuang, F. and Galiana, F.D. (1990). Unit commitment by simulated annealing. IEEE Transactions on Power Systems, 5(1), 311-318.