在現在的測試環境中，測試向量的品質是以它的fault coverage 來決定，fault coverage 愈接近100%就代表這組測試向量的品質愈好，但隨著深次微米的製程技術愈來愈進步，每一個電晶體愈來愈微小，傳統的stuck at fault 模型已經漸漸的不符合真實的晶片瑕疵情況了。在史丹佛大學的可靠計算中心有實驗證明顯示，100%的fault coverage 並不能代表很高比例的晶片瑕疵，當然測試向量也不能偵測到這些瑕疵。於是我們必需把fault model 的建立從gate level 更往下降到比較接近實際的情形的transistor level，其至於是physical level。
在本篇論文中, 我們成功地發展了一種瑕疵的模型法。這個模型法直接從電路的佈局圖上著手，將最可能發生的短路瑕疵，透過『蝴蝶型結構』萃取的方式與SPICE 模擬，轉成一個等效的邏輯電路圖。在這個過程中，原本因短路瑕疵而常發生的類比准位的問題可以迎刃而解，不管是瑕疵診斷或是測試也好，都可以在傳統的邏輯電路層面進行分析。我們已經將這一整套方法實現為一個自動化的系統，不但可以產生電路中每一個邏輯閘的最可能瑕疵模型，也可以自動化產生覆蓋率接近100% 的測試向量。

In this thesis we investigate a defect modeling and testing methodology for intra-cell bridging defects from the layout perspective. For defect modeling, we incorporate a butterfly-based faulty schematic extraction and SPICE simulation to resolve the potential analog effect a bridging defect may cause. By doing so, a more realistic faulty circuit at the gate level can thus be generated for each defect under consideration. For defect coverage simulation and test vector generation, we further convert the defect detection requirements into a circuit form and then piggyback on traditional ATPG tools. Experimental results indicate that simple stuck-at test set can only achieve 86% defect coverage, while our method can further boost it to almost
100% for ISCAS85 benchmark circuits.

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