在通訊系統中，為達到高可靠、高品質、高效率傳輸能力，錯誤更正碼扮演著重要的角色。錯誤更正碼已經廣泛的應用在有線通訊、無線通訊與許多的儲存系統中。通過有結構特性的編碼和具效率的解碼技術，可以有效的降低位元之錯誤率，進而降低傳輸所需要的功率。錯誤更正碼技術已日漸受到重視，並被認為是達成高可靠、高品質及高效率通訊鏈路構連之有效途徑。作為錯誤更正碼的一種，低密度奇偶檢查碼的顯著的解碼效果和硬體的平行度架構設計的優勢，也讓它廣泛的應用於不同的通訊系統上。對一個高吞吐量之低密度奇偶檢查碼解碼器而言，我們將其變數節點分成幾個群組並且循序的處理它們。使用高平行度架構，在第k次的遞迴裡可能將使用第(k-2)次遞迴的訊息來更新而不是使用第(k-1)次的，而為了避免這類型的資料相依則需要閒置周期。為了解決邏輯面積提高的問題，我們提出了部分位元比較架構和兩階段比較運算單元來減少邏輯面積。根據我們的架構與排程，這個高吞吐量之低密度奇偶檢查碼解碼器在遞迴時將不需要閒置周期，而且跟其他現存的低密度奇偶檢查碼在相同效能的比較上也需要較少的周期。一個(8192, 7171)基於里德所羅門碼的低密度奇偶檢查碼，碼率為0.8753的解碼器被以CMOS 90奈米技術實現。與現存最新的解碼器比較起來，這個原創的解碼器在相同的位元錯誤率效能上能達到足可比較的硬體效能，也可以在12次的遞迴裡可以達到最高的吞吐量(40.6Gb/s)。使用提早終止解碼機制之下，吞吐量將會在8次的遞迴內提高到60.9Gb/s。

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