隨著積體電路製程不斷微縮，在90 nm製程之後能使用於嵌入式非揮發性記憶體衍生出電容耦合，氧化層漏電，軟性崩潰等等問題，無法有效隨著製程縮小其尺寸，目前尚無真正有效的解決方法。在國際論文中，大多嘗試以新的架構取代原有的堆疊式記憶體，然而其解決方式的技術難度過高。在本篇論文中，將提出一完全符合邏輯製程步驟的新式非揮發式記憶體，此架構已經130 nm、90 nm製程世代驗證，本論文將其概念實現於45 nm與32 nm等前瞻性邏輯製程步驟，提供嵌入式非揮發性記憶體元件另一種選擇考量。
本研究中所提出的元件，無須特殊製程與光罩步驟，採用電晶體本身既有的間隙壁結構，以兩電晶體串聯方式產生自我對準氮化矽儲存層，提供電荷儲存。元件在寫入機制上採用源極注入，可有效率的將熱電子注入儲存層中，並利用二維製程與電性模擬軟體驗證分析元件基本特性，在先進製程中，更可實現以帶對帶穿隧寫入機制達到抹除的效果，進一步達到多次寫入抹除的可能性。此記憶體結構相對於傳統記憶體，在製作成本與元件縮小性上有相當大的改進及優勢。

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