在半導體產業持續不斷的發展下，半導體元件的尺寸已經達到了物理上的極限，因此在未來研究的道路上，新興材料的開發是不可或缺的。鍺擁有較於傳統半導體產業慣用的材料－矽，還要高很多的電子與電洞遷移率，因此在近年來，有許多的研究開始探討鍺的電晶體特性及可靠度，是否在未來有機會能夠取代矽成為半導體市場的新寵兒。然而，在如此競相開發鍺元件應用的當下，卻鮮少有研究探討以鍺作為通道的非揮發記憶體，假如在未來研究的道路上，市面上的產品中，鍺的應用漸漸增加，鍺的其他應用也會日漸重要，所以鍺記憶體的開發必然是不可或缺的。在記憶體產業中，非揮發性記憶體主要是用於儲存積體電路中的重要資料，除此之外，嵌入式記憶體擁有相較於傳統記憶體簡單的製程，由於與電晶體相差無異的製程，在元件製作上更容易能夠與積體電路做整合。本論文內容主要是在探討新興材料－鍺結合嵌入式非揮發性記憶體的研究，利用鍺材料作為通道，結合以前實驗室有成功發表的嵌入式記憶體結構，利用ＦＮ穿隧的寫入抹除方式以及BBHE的寫入方式去探討基本記憶體的儲存特性，除此之外，更去比較電容耦合比例對於元件的寫入速度的差異性，及其可靠度的分析。

In the recently years, the rise of semiconductor industry is driving the development of electrical industrial market. however, the conventional transistors face many challenges beyond 5nm node, such as the physic limitation of the lithography and the quantum physic effect, etc. Therefore, the develop of new material is indispensable in the future.

Germanium is a material which mobility is much higher than silicon, in the recently years, germanium transistors have been demonstrated and studied for new-generation application, but there are few research talks about germanium memory.

In this thesis, we successfully demonstrate embedded non-volatile memory with germanium material, this germanium material was deposited on SOI substrate by reduced-pressure chemical vapor deposition (RP-CVD). Because of the special structure, the process of the germanium memory is the same as the transistor device, unlike the conventional memory device, tunneling oxide and blocking oxide were deposited at the same time. Thicker gate oxide layer brings bad influence on transistor characteristics, it is helpful for germanium memory, germanium is very sensitive to high temperature; the less process fabrication can preserve more process thermal budget for the rest fabrication.

In the later chapter, we will introduce the characteristics of Germanium FinFET Structure on Twin Transistor Non-Volatile Memory. This device shows us the good programming and erasing memory window, the memory window still maintains more than 50% after 103 P/E cycles operation, and the storage electron can be store inside the tapping layer more than ten years in 85oC environment, it is good enough for memory application.

Chapter 1
[1-1] IBM’s roadmap for 14nm, 10nm and 7nm
[1-2] International Roadmap for Devices and Systems (IRDS™) 2017 Edition
[1-3] MORE MOORE S. Takagi et al., "Carrier-Transport-Enhanced Channel CMOS for Improved Power Consumption and Performance," IEEE Transactions on Electron Devices, vol. 55, no. 1, pp. 21-39, 2008.
[1-4] J. Feng, R. Woo, S. Chen, Y. Liu, P. B. Griffin, and J. D. Plummer, "P-Channel Germanium FinFET Based on Rapid Melt Growth," IEEE Electron Device Letters, vol. 28, no. 7, pp. 637-639, 2007.
[1-5] B. Liu et al., "High-Performance Germanium$\Omega$-Gate MuGFET With Schottky-Barrier Nickel Germanide Source/Drain and Low-Temperature Disilane-Passivated Gate Stack," IEEE Electron Device Letters, vol. 33, no. 10, pp. 1336-1338, 2012.
[1-6] C. Chung, C. Chen, J. Lin, C. Wu, C. Chien, and G. Luo, "First experimental Ge CMOS FinFETs directly on SOI substrate," in 2012 International Electron Devices Meeting, 2012, pp. 16.4.1-16.4.4.
[1-7] Y. Nakakita, R. Nakakne, T. Sasada, M. Takenaka, and S. Takagi, "Interface-Controlled Self-Align Source/Drain Ge p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors Fabricated Using Thermally Oxidized GeO2Interfacial Layers," Japanese Journal of Applied Physics, vol. 50, p. 010109, 2011/01/20 2011.
[1-8] R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti, "Introduction to flash memory," Proceedings of the IEEE, vol. 91, no. 4, pp. 489-502, 2003.
[1-9] N. D. Young, G. Harkin, R. M. Bunn, D. J. McCulloch, and I. D. French, "The fabrication and characterization of EEPROM arrays on glass using a low-temperature poly-Si TFT process," IEEE Transactions on Electron Devices, vol. 43, no. 11, pp. 1930-1936, 1996.
[1-10] L. Jin-Woo, L. Nae-In, C. Hoon-Ju, and H. Chul-Hi, "Improved stability of polysilicon thin-film transistors under self-heating and high endurance EEPROM cells for systems-on-panel," in International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217), 1998, pp. 265-268.
[1-11] Y. Wu, P. Su, C. Chang, and M. Hung, "Novel Twin Poly-Si Thin-Film Transistors EEPROM With Trigate Nanowire Structure," IEEE Electron Device Letters, vol. 29, no. 11, pp. 1226-1228, 2008.
[1-12] Y.-H. Wu, J.-R. Wu, M.-L. Wu, L. Chen, and C.-C. Lin, Ge-Based Nonvolatile Memory Formed on Si Substrate with Ge-Stabilized Tetragonal ZrO2 as Charge Trapping Layer. 2011, p. H410.
[1-13] M. Yeh et al., "Comprehensive Study of N-Channel and P-Channel Twin Poly-Si FinFET Nonvolatile Memory," IEEE Transactions on Nanotechnology, vol. 13, no. 4, pp. 814-819, 2014.
[1-14] M.-S. Yeh et al., "A single poly-Si gate-all-around junctionless fin field-effect transistor for use in one-time programming nonvolatile memory," Nanoscale Research Letters, vol. 9, no. 1, p. 603, 2014/11/06 2014.
[1-15] M.-S. Yeh et al., "Fabrication, characterization and simulation of Ω-gate twin poly-Si FinFET nonvolatile memory," Nanoscale Research Letters, vol. 8, no. 1, p. 331, 2013/07/22 2013.
Chapter 2
[2-1] P. Pavan, R. Bez, P. Olivo, and E. Zanoni, "Flash memory cells-an overview," Proceedings of the IEEE, vol. 85, no. 8, pp. 1248-1271, 1997.
[2-2] Sze, Simon M., and Kwok K. Ng. Physics of semiconductor devices. John wiley & sons, 2006.
[2-3] M. Lenzlinger and E. H. Snow, "Fowler‐Nordheim Tunneling into Thermally Grown SiO2," Journal of Applied Physics, vol. 40, no. 1, pp. 278-283, 1969/01/01 1969.
[2-4] P. Cappelletti, R. Bez, D. Cantarelli, and L. Fratin, Failure mechanisms of flash cell in program/erase cycling. 1995, pp. 291-294.
[2-5] 2008_Nonvolatile Memory Technologies with Emphasis on Flash edited by Mr. Joe E. Brewer Master of Science degree in Electrical Engineering, Dr. Manzur Gill Ph.D. in Electrical Engineering,
[2-6] R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti, "Introduction to flash memory," Proceedings of the IEEE, vol. 91, no. 4, pp. 489-502, 2003.
Chapter 3
[3-1] M. Yeh et al., "Ge FinFET CMOS Inverters With Improved Channel Surface Roughness by Using In-Situ ALD Digital O3 Treatment," IEEE Journal of the Electron Devices Society, vol. 6, pp. 1227-1232, 2018.
[3-2] Q. Xie et al., "Germanium surface passivation and atomic layer deposition of high-kdielectrics—a tutorial review on Ge-based MOS capacitors," Semiconductor Science and Technology, vol. 27, no. 7, p. 074012, 2012/06/22 2012.
[3-3] M. Botzakaki et al., Interfacial Properties of ALD-Deposited Al2O3/p-Type Germanium MOS Structures: Influence of Oxidized Ge Interfacial Layer Dependent on Al2O3 Thickness. 2012, p. 32.
[3-4] E. Shigesawa et al., "Study on Al2O3/Ge interface formed by ALD directly on epitaxial Ge," Semiconductor Science and Technology, vol. 33, no. 12, p. 124020, 2018/11/20 2018.
[3-5] R. Degraeve et al., "Trap Spectroscopy by Charge Injection and Sensing (TSCIS): A quantitative electrical technique for studying defects in dielectric stacks," in 2008 IEEE International Electron Devices Meeting, 2008, pp. 1-4.
[3-6] Y. Lee et al., "Dopant Activation in Single-Crystalline Germanium by Low-Temperature Microwave Annealing," IEEE Electron Device Letters, vol. 32, no. 2, pp. 194-196, 2011.
Chapter 4
[4-1] L. Milani, F. Torricelli, and Z. M. Kovács-Vajna, "Single-Poly-EEPROM Cell in Standard CMOS Process for Medium-Density Applications," IEEE Transactions on Electron Devices, vol. 62, no. 10, pp. 3237-3243, 2015.
[4-2] Joe E. Brewer and Manzur Gill, Nonvolatile Memory Technologies with Emphasis on Flash, 1st ed., IEEE press, 2008, ch. 13, pp.623.