簡易檢索 / 詳目顯示

研究生: 陳俊甫
Chun-Fu Chen
論文名稱: 嵌入式自我校正晶片間不規則排列應用於太空感測器
Built-In Self-Repair for Die-to-Die Misalignment of Space Sensors
指導教授: 黃錫瑜
Shi-Yu Huang
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2006
畢業學年度: 94
語文別: 英文
論文頁數: 51
中文關鍵詞: 太空影像感測器嵌入式自我校正晶片不規則排列
外文關鍵詞: CMOS image sensor, space sensor, Built-In Self-Repair, misalignment
相關次數: 點閱:4下載:0
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • 在太空遠端觀測系統中,數位影像感測器扮演一個重要角色,感測元件可以分成兩大主流:電子耦合式(CCD)或互補式金氧半導體式數位影像感測器(CMOS Image Sensor),前者往往受限於進出口限制不易取得,且後者在國內半導體廠有完整的製成技術可以支援及加上低功率、整合性高等優點,互補式金氧半導體式數位影像感測器日漸重視,而對於太空影像感測器而言,感測元件是以長條的排列來得到較寬廣的感測視野。而受限於製成上面的限制,長條形的影像感測器通常是由數個晶片在基板上肩並肩的佈局組裝完成。可是受限於組裝機器的對齊精密度,要將晶片與晶片彼此水平並平沒有誤差是非常困難的。如此不規則排列會對於影像上造成失真,特別是應用於高精確度的太空影像也會造成往後的分析、應用上有所誤差。
    對於這樣的問題,在這篇論文中我們應用一個嵌入式自我校正(Built-In Self-Repair)的方法來處理。首先,我們利用數學上的餘旋相似度(Cosine Similarity)來計算出兩個晶片間不規則的誤差。利用計算後的誤差量可以幫助我們將失真的影像作即時的校正。在校正的方式是利用感測後的影像會寫入一個可隨機存取的記憶體,利用調整記憶體寫入的位置來修補失真的影像。我們模擬的結果表示晶片間不規則排列的誤差量可以分之百的計算出且造成的影像失真可以正確的修補。對於整個嵌入式自我校正的模組可以相容原本的影像感測器及周邊記憶體電路,整體的模組面積相較於VGA格式的記憶體空間也只有3.29%。


    A space sensor often consists of a number of dies integrated in a side-by-side manner on a single packaging substrate due to its high-resolution requirement. The alignment of these dies, i.e., placement of the dies so that their respective sensor cells can align horizontally, is highly challenging. Even with high-precision instruments, die-to-die misalignment may still exist. To overcome this problem, we investigate in this thesis a Built-In Self-Repair scheme. We first decide how big the misalignment is for each die-to-die boundary using the concept of cross-correlation. Once the misalignment size is decided, the information is used to repair the distorted image by simply modifying the addressing of the image buffer. Simulation indicates that the misalignment can be repaired nicely for hundreds of test images with almost 100% successful rate. The proposed BISR scheme can be built as a simple collar circuit around the image buffer. The layout shows only 3.29% area overhead for a VGA-resolution test circuit.

    Abstract …………………………………………………………………1 Contents …………………………………………………………………2 List of Figures…………………………………………………………5 List of Tables …………………………………………………………8 Chapter 1 Introduction ………………………………………………9 1.1 Motivation…………………………………………………………10 1.2 Thesis Organization ……………………………………………13 Chapter 2 Preliminaries ……………………………………………14 2.1 Linear Pixel Array………………………………………………15 2.2 Correlated Double Sampling Circuitry………………………16 2.3 Pipelined Analog to Digital Converter ……………………16 2.4 Controller…………………………………………………………17 Chapter 3 Built-In Self-Repair System …………………………19 3.1 Cosine Similarity Function……………………………………19 3.2 BISR System Flow…………………………………………………21 3.2.1 Misalignment Detection …………………………………22 3.2.2 Distortion Cancellation ………………………………25 Chapter 4 Hardware Implementation ………………………………28 4.1 BISR Hardware Block Diagram …………………………………28 4.2 Hardware Reduction………………………………………………28 4.3 Application to a Space Sensor ………………………………33 Chapter 5 Experimental Results……………………………………37 5.1 Simulation Result of Circuits ………………………………37 5.1.1 SRAM buffer…………………………………………………37 5.1.2 Misalignment Detector……………………………………37 5.1.3 Bookkeeping Registers……………………………………39 5.1.4 Distortion Cancellation…………………………………40 5.2 BISR System Performance ………………………………………40 5.2.1 Misalignment Detection Success Rate Analysis ……40 5.2.2 Window Size ………………………………………………41 5.2.3 The Space Sensor and BISR Specification …………43 5.2.4 BISR Layout View ………………………………………44 5.2.5 BISR Simulation Results ………………………………45 Chapter 6 Conclusion ………………………………………………48 Bibliography …………………………………………………………49

    [1] M. Nakagawa, and R. Shibasaki, “Integrating High Resolution Air Borne Linear CCD (TLS) Imagery and LIDAR data,” Proc. of Remote Sensing and Data Fusion over Urban Areas, 2nd GREE/ISPRS Joint Workshop, pp. 236-240, May 2003.

    [2] D. Poli, “Georeferencing of Multi-line CCD Array Optical Sensors with A General Photogrammetric Model,” Proc. of 2003 IEEE Geoscience and Remote Sensing Symposium (GRSS) Vol. 6, pp. 3908-3910, July 2003.

    [3] S. Ohba, M. Nakai, M. Aoki, S. Shimada, K. Uchiumi, M. Fujita, and M. Kubi, “A 1024 Element Linear CCD Photo Sensor with Unique Photodiode Structure,” IEEE Transactions on Electron Devices, Vol. 27, No. 9, pp. 1804-1808, Sept. 1998.

    [4] R. H. Nixon, S. E. Kemeny, B. Pain, C. O. Staller, and E .R. Fossum, “256×256 CMOS Active Pixel Sensor Camera-on-a-chip,” IEEE Journal of Solid-State
    Circuits, Vol. 31, No. 12, pp. 2046-2050, Dec. 1996.

    [5] E. R. Fossum, “CMOS Image Sensor: Electronic Camera-On-A-Chip,” IEEE Transactions on Electron Devices, Vol. 44, pp. 1689-1698, Oct. 1997.

    [6] A. Flsh, A. Belenky, and O. Yadid-Pecht, “Wide Dynamic Range Snapshot APS for Ultra Low Power Application,” IEEE Trans. on Circuit and Systems, Vol. 52, No. 11, pp. 739-733, Nov. 2005.

    [7] M. Mitsuyoshi, K. Motonari, K. Shigetaka, M. Takahiko, and Y. Takumi “1/4-Inch 2-Mpixel MOS Image Sensor with 1.75 Transistors/Pixel” IEEE Journal of Solid-State Circuits, Vol. 39, No. 12, pp. 2426-2430, Dec. 2004.

    [8] B.-R. Lin, S.-Y. Huang, C.-H. Lai, and Y.-C. King, “A High Dynamic Range CMOS Image Sensor Design Based On Two-Frame Composition,” Proc. of Int’l System-on-Chip Conf., pp. 389-392, Sept. 2003.

    [9] O. Yadid-Pecht and E. Fossum, “Wide Instance Dynamic Range CMOS APS Using Dual Sampling,” IEEE Transactions on Electron Devices, Vol. 44, pp. 1721-1723, Oct. 1997.

    [10] S.-F. Chen, Y.-J. Juang, S.-Y. Huang, and Y.-C. King, “Logarithmic CMOS Image Sensor through Multi-Resolution Analog-To-Digital Conversion,” Proc. of IEEE Int’l Symp. on VLSI Technology, Systems, and Applications (VLSI-TSA), pp. 227-230, April 2003.

    [11] N. Akahana, S. Sugaa, S. Adachi, K. Mori, T. Ishiuchi, and K. Mizobuchi, “A Sensitivity and Linearity Improvement of a 100db Dynamic Range CMOS Image Sensor Using A Lateral Overflow Integration Capacitor,” IEEE Journal of Solid-State Circuits, Vol. 41, No. 4, pp. 851-858, April 2006.

    [12] L.-W. Lai, and Y.-C. King, “A Novel Logarithmic Response CMOS Image Sensor with High Output Voltage Swing and In-Pixel Fixed Pattern Noise Reduction,” Proc. of 2002 IEEE Asia-Pacific Conference, pp. 105-108, Aug. 2002.

    [13] K. Yonemoto and H. Sumi, “A CMOS Image Sensor with A Simple Fixed-Pattern Noise Reduction Technology and A Hole Accumulation Diode,” IEEE Journal of Solid-State Circuit, Vol. 35, No. 8, pp. 1146-1152, Dec. 2000.

    [14] J. Karasawa, M. Segawa, Y. Kishimoto, M. Aoki, and T.Sasaki, “Flip Chip Interconnection Method Applied to Small Camera Module,” Proc. of Electronic Components and Technology Conf., pp. 1024-1028, June 2001.

    [15] T. Li, “Electro-Optical Sensor Packaging Overview,” Proc. of 94 Southcon Conf., pp. 134-137, March 1994.

    [16] P. E. Allen, and D. R. Holberg, “CMOS Analog Circuit Design,” 2nd, OXFORD University Press, Inc., pp. 691-697, 2002.

    [17] Philips Semiconductor, “The I2C Bus Specification Version 2.1,” 2000.

    [18] K. K. Parhi, “VLSI Digital Signal Processing System Design and Implementation,” John Wily & Sons, Inc. pp. 149-174, 1996.

    [19] Instrument Technology Research Center (ITRC), National Applied Research Laboratory, Taiwan.

    [20] E. Garcia, “An Information Retrieval Tutorial on Cosine Similarity Measures, Dot Products and Term Weight Calculations,” Mi Islita Website, 21 Oct. 2005.

    無法下載圖示 全文公開日期 本全文未授權公開 (校內網路)
    全文公開日期 本全文未授權公開 (校外網路)

    QR CODE