本研究首次實現三維耦合陣列之微機電共振器與振盪器，我們基於CMOS-MEMS標準製程成功將過去開發之CMOS-MEMS垂直耦合(Vertically Coupled, VC)共振器[1]展延至三維耦合形貌，並結合同平台之0.35 m CMOS介面電路實現單晶片微機械電路。三維共振器陣列的設計為側向連結9對垂直耦合共振器(N = 18, N代表著組成陣列之共振器的數目)，量測結果得到其共振頻位在5.64 MHz，且品質因數Q為1,092。我們比較九對(N = 18)陣列(亦即三維耦合陣列)與單對(N = 2)之垂直耦合共振器，三維耦合陣列透過電極的設計配置能夠完全地消除馬鞍型(Saddle, SA)模態[2] (非目標之模態)，但仍有其他Spurious Modes位於垂直耦合共振模態附近。在同樣的直流偏壓下三維耦合陣列相較單對元件具有較佳之功率負載能力。本研究亦整合Lock-in + PLL電路系統，使三維耦合陣列式振盪器成功起振，根據量測結果，四對垂直耦合共振對陣列相較單對降低了6 dB的相位雜訊，我們期待此技術未來能帶來更多功能及應用，如傳統積體電路的發展歷程一般，朝向中型微機械積體電路 (Medium-Scale Integrated Micromechanical Circuits, MSI)方向邁進。

A 3-D mechanically-coupled resonator array has been demonstrated for the first time using CMOS-MEMS technology. A high-performance vertically-coupled (VC) CMOS-MEMS resonator pair is utilized to extend the array topology into 3-D configuration with on-chip interfaced circuit through a TSMC 0.35 μm 2P4M CMOS-MEMS platform. An array design of 9 VC pairs (N = 18 where N is the number of constituent resonators of an array) was fabricated and characterized with resonance frequency of 5.64 MHz and Q-factor of 1,092. As compared to a single VC pair (N = 2), the Saddle (SA) mode (undesired mode) is eliminated in the array design by the use of electrode phasing [2] at the cost of weak spurious modes around the desired resonance. Under same dc biasing, the proposed 3-D array achieves better power handling over the single VC pair. The 3-D array oscillator was also realized by using an instrumental Lock-in + PLL system. It reveals that the 4-VC SPR array features a 6-dB in-band phase noise improvement as compared to the single one. This technology is expected to bring more functionalities towards medium-scale integrated (MSI) micromechanical circuits.

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