研究生: |
黃洛維 Huang, Lo-Wei |
---|---|
論文名稱: |
應用於紅外線感測器陣列之1.8伏自動轉換增益讀出電路 A 1.8V Readout Integrated Circuit with Adaptive Transimpedance Control Amplifier for IR Focal Plane Arrays |
指導教授: |
謝志成
Hsieh, Chih-Cheng |
口試委員: |
謝志成
邱進峰 洪浩喬 鄭桂忠 |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
論文出版年: | 2011 |
畢業學年度: | 100 |
語文別: | 中文 |
論文頁數: | 124 |
中文關鍵詞: | 自動轉換增益 、紅外線感測器陣列 、電容反饋跨阻抗放大器 、讀出電路 、動態範圍 |
外文關鍵詞: | Adaptive Transimpedance Control, IR Focal Plane Arrays, Capacitive Transimpedance Amplifier, Readout Integrated Circuit, Dynamic Range |
相關次數: | 點閱:2 下載:0 |
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本論文提出並分析新型含有自動適當轉換技術之讀出電路設計與技巧製作,運用在紅外線偵測器陣列光訊號讀出之積體電路晶片。此提出的自動適當轉換技術架構含有自動回饋積分電容之前級放大器,放大器之類比訊號會藉由比較器產生出回饋的數位訊號(S0~S1)使積分電容陣列產生相對應的開關切換,可涵蓋從暗部到亮部的大反差背景範圍,使影像具有廣泛的動態範圍,避免因降低操作電壓所導致動態範圍減少的問題。電容反饋跨阻抗放大器(Capacitive Transimpedance Amplifier)可以降低寄生電容對小積分電容的影響且利用小積分電容提供紅外線偵測器高感光的感應度,利用放大器虛短路原理提供恆定的感測器偏置電壓降低雜訊以及漏電流的影響;此外在放大器輸出端使用了雙重相關取樣(Correlated Double Sample)電路,減少並消除讀出電路中固定樣式雜訊、時脈回饋雜訊、通道電荷注入和共模雜訊。
紅外線感測器讀出陣列為32 x 32且像素大小為30 x 30um2的讀出晶片使用0.18新型互補式金氧半技術設計並完成晶片研製,操作在電壓1.8V工作電壓,其量測結果成功驗證了讀出晶片的功能及效能。晶片尺寸為1.8mmx1.8mm。其可增進24dB的動態範圍、畫面速率為175 fps、像素功率消耗為5μW/像素、晶片功率消耗為5.5mW。此高效能讀出電路具有高感光感應度、廣泛動態範圍、低功率消耗等優點,可適用於大範圍亮度與高對比影像讀出的運用。
In this thesis, a readout integrated circuit (ROIC) with adaptive transimpedance control (ATC) amplifier for Infrared Focal Plane Arrays (IR FPAs) is presented. The proposed ATC readout circuit consists of a front-end transimpedance amplifier (TIA) with an adaptive feedback capacitance. The output signal is fed to a comparator which determines a set of gain code (S0~S1) to control the feedback capacitance selected from a capacitor array. The capacitive transimpedance amplifier (CTIA) provides a stable bias for low-noise and low-leakage operation of IR sensor. It has the advantages in noise rejection, gain control, dynamic range, uniformity, and linearity. The column-shared Correlated Double Sample (CDS) circuit is utilized to eliminate the KTC noise and offset non-uniformity of the readout circuit.
A CMOS image sensor chip with 32 x 32 pixel array and 30 x 30μm2 pixel size has been designed and fabricated in 0.18μm CMOS technology. The functions and superior readout performance of the proposed ATC readout circuit have been verified by experimental measurement at 1.8V supply. The chip area occupies 1.8 mm x 1.8 mm. It achieves a 24dB improvement of dynamic range, a frame rate of 175 fps, a power-per-pixel of 5μW/pixel and the total power of 5.5mW, respectively. It is shown that a high-performance readout circuit for IRFPA with high charge sensitivity, widely dynamic range and low power is realized. These advantageous traits make the readout circuit suitable for the various applications.
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