本實驗中，我們使用射頻磁控濺鍍法沈積La2O3薄膜，所得到的結果顯示絕緣層厚度為8, 15, 19和35 nm，在電晶體的特性、依時性界電崩潰及電流機制的分析，皆有加以研究及探討。而La2O3薄膜具有良好的電性特徵，如效小的等效厚度、漏電流小、表面平坦度佳，而且在500℃快速熱退火後並沒有介面層的產生。
我們成功地製作了N通道的金屬（Al）/氧化鑭（La2O3）/半導體（p-Si）的場效電晶體，臨界電壓約在0.2V，最小的次臨界斜率是114 mV/dec.，在VD=0.05V下，ION/IOFF的比例有5個數量級之多，顯示電晶體有不錯的電流切換能力。經由次臨界斜率St=2.3(kT/q)[1+(CD+Cit)/Cox]的計算，可以得到界面缺陷電荷密度（Dit）為3.36x1012 cm-2-eV-1，而電子的遷移率為399cm2/V-s。
等效厚度為2.9nm的Al/ La2O3/ p-Si界面間的電流傳導機制在溫度450K~550K為蕭基發射所主導，所得到的Al/ La2O3的蕭基能帶高為1.22 eV及電子的有效質量為0.104m0。
本實驗中，我們探討了崩潰電壓的分佈、偉伯斜率、面積比例因素。在等效厚度為2.9nm和1.2nm所淬取出的偉伯斜率分別為6.4和2.9。而崩潰的主要機制為所施加應力所產生的固定電荷而形成漏電流路徑，Percolation model是第一次用來解釋Al/ La2O3/ p-Si 電容結構的崩潰模型。此外，推算面積在4x10-4cm2的十年存活時間為-4.8V。

High quality La2O3 gate dielectrics were deposited by RF magnetron sputtering with thickness of 8 nm, 15 nm, 19 nm and 35 nm. In this work, transistor characteristics, TDDB and conduction mechanism have been discussed. La2O3 showed excellent electrical properties, such as small equivalent thickness, low leakage current, smooth film surface and no interfacial layer with rapid thermal annealing (RTA) at 500℃.
N-channel metal-oxide-semiconductor field effect transistors (MOSFETs) using La2O3 gate oxide were fabricated successfully. The minimum threshold voltage was 0.1V and subthreshold swing is 114 mV/dec. The ION/IOFF ratio is about 105 at VD=0.05V. Since St=2.3(kT/q)[1+(CD+Cit)/Cox], the interface trapped charge density Dit is extracted to be about 3.36x1012 cm-2-eV-1. Field effect electron mobility is about 399cm2/V-s.
The dominant conduction mechanism of the Al/La2O3/p-Si metal-lanthanum oxide-semiconductor capacitor is Schottky emission at high temperatures from 450K to 550K. The extracted Al/ La2O3 barrier-height and effective electronic mass in 2.9 nm EOT La2O3 films are about 1.22eV and 0.104m0, respectively.
Breakdown voltage distributions, Weibull slope, area-scaling factors, have been investigated for La2O3 gate dielectric. The extracted Weibull slope β for different thicknesses (EOT=2.9 nm, 1.2 nm) of the breakdown distribution is found to be 6.4 and 2.6, respectively. And breakdown mechanism is caused by stress-induced charge traps. Percolation model is proposed to explain La2O3 gate dielectric breakdown for the first time. The estimated ten-year lifetime for a capacitor area of 4x10-4cm2 is projected to be -4.8V.

[1] H. S. Momose, M. Ono, T. Yoshitomi, T. Ohguro, S. Makamura, M. Saito, and H. Iwai, “1.5 nm direct-tunneling gate oxide Si MOSFET’s,” IEEE Trans. Electron Devices, vol. 43, pp. 1233–1241, August 1996.
[2] J. L. Autran, R. Devine, C. Chaneliere, and B. Balland, “Fabrication and characterization of Si-MOSFET’s with PECVD amorphous Ta2O5 gate insulator,” IEEE Electron Device Lett., vol. 18, pp. 447–449, September 1997.
[3] C. Chaneliere, S. Four, J. L. Autran, R. A. B. Devine, and N. P. Sandler, “Properties of amorphous and crystalline Ta2O5 thin films deposited on Si from Ta(OC2H5)5 precursor,” J. Appl. Phys., vol. 83, no. 9, pp. 4823-4829, May 1998.
[4] Q. Lu, D. Park, A. Kalnitsky, C. Chang, C. C. Cheng, S. P. Tay, T. J. King, and C. Hu, “Leakage Current Comparison Between Ultra-Thin Ta2O5 Films and Conventional Gate Dielectrics,” IEEE Electron Device Lett., vol. 19, no. 9, pp. 341-342, September 1998.
[5] D. Park, Y. King, Q. Lu, T. J. King, C. Hu, A. Kalnitsky, S. P. Tay, and C. C. Cheng, “Transistor Characterization with Ta2O5 Gate Dielectric,” IEEE Electron Device Lett., vol. 19, no. 11, pp. 441-443, November 1998.
[6] B. C. Lai, N. Kung, and J. Y. Lee, “A study on the capacitance-voltage characteristics of metal-Ta2O5-silicon capacitors for very large scale integration metal-oxide-semiconductor gate oxide applications,” J. Appl. Phys., vol. 85, no. 8, pp. 4087-4090, April 1999.
[7] J. C. Yu, B. C. Lai, and J. Y. Lee, “Fabrication and Characterization of Metal-Oxide-Semiconductor Field-Effect Transistors and Gated Diodes Using Ta2O5 Gate Oxide,” IEEE Electron Device Lett., vol. 21, no. 11, pp. 537-539, November 2000.
[8] B. C. Lai, J. C. Yu, and J. Y. Lee, “Ta2O5/Silicon Barrier Height Measured from MOSFETs Fabrication with Ta2O5 Gated Dielectric,” IEEE Electron Device Lett., vol. 22, no. 5, pp. 221-223, May 2001.
[9] Y. H. Wu, and A. Chin, “Electrical Characteristics of High Quality La2O3 Gate Dielectric with Equivalent Oxide Thickness of 5 Ả,” IEEE Electron Device Lett., vol. 21, no. 7, pp.341-343, July 2000.
[10] J. R. Hauser, Tech. Dig. Int. Electron Device Meeting, Short Course on Sub-100nm CMOS, IEEE, Piscataway, NJ, 1999.
[11] M. J. Kelly, and D. B. Terry, “Properties of La-silicate high-K dielectric films formed by oxidation of La on silicon,” J. Appl. Phys., vol. 93, pp. 1691-1696, February 2003.
[12] J. H. Jun, C. H. Wang, and D. J. Won, “Structural and Electrical Properties of a La2O3 Thin Film as a Gate Dielectric,” Journal of the Korea Physical Society, vol. 41, no. 6, pp. 1-5, December 2002.
[13] S. Ohmi, and C. Kobayashi, “Characterization of La2O3 and Yb2O3 Thin Films for High-K Gate Insulator Application,” Journal of Electrochemical Society, vol. 150, no. 7, pp. F134-F140, 2003.
[14] Iwai, H. Ohmi, S. Akama, S. Ohshima, C. Kikuchi, A. Kashiwagi, I. Taguchi, J. Yamamoto, H. Tonotani, J. Kim, Y. Ueda, I. Kuriyama, and A. Yoshihara, “Advanced gate dielectric materials for sub-100 nm CMOS,” IEEE Electron Device Meeting, 2002, 8-11, pp.625-628, December 2002.
[15] Y. Kim, A. Kuriyama, Isao Ueda, S. Ohmi, K. Tsutsui, and H. Iwai, “Analysis of Electrical Characteristics of La2O3 Thin Films Annealed in Vacuum and Others,” ESSDERC 2003, vol. 16, pp. 569-572, 2003.
[16] F. C. Chiu, H. W. Chou, and Joseph Ya-min Lee, “Electrical conduction mechanism of metal/ La2O3/Si structure,” J. Appl. Phys., vol. 97, p. 103503, May 2005.
[17] K. J. Hubbar, and D.G. Schlom, “Thermodynamic stability of binary oxides in contact with silicon,” J. Mater. Res., vol. 11, no. 11, pp. 2757-2776, Nov 1996.
[18] MRS BULLETIN, “Alternative Gate Dielectrics for Microelectronics”, vol. 27, no. 3, March 2002.
[19] S. M. Sze, Physics of Semiconductor Device, 2nd ed., Wiley, New York, 1981.
[20] D. K. Schroder, Semiconductor Material and Device Characteristics, Wiley, Arizona, 1998.
[21] K.C. Kao, and W. Hwang, Electrical Transport in Solids, Pergamon, New York, 1981.
[22] P. Mark, and W. Helfrich, “Space-Charge-Limited Currents in Organic Crystals,” J. Appl. Phys. vol. 33, p.205, 1965.
[23] M. A. Lampert, and P. Mark, Current Injection in Solids, Academic, New York, 1970.
[24] M. A. Lampert, “Simplified Theory of Space-Charge-Limited Currents in an Insulator with Traps,” Phys. Rev. vol. 103, p.1648, 1956.
[25] K. Chen, H. C. Wann, J. Dunster, P. K. Ko, and C. Hu, “MOSFET Carrier Mobility Model Based on Gate Oxide Thickness, Threshold Voltage and Gate Voltages,” Solid-State Electronics, ” vol. 39, no. 10, pp. 1515-1518, 1996.
[26] D. K. Schroder, Semiconductor Material and Device Characteristics, Wiley, Arizona, 1998.
[27] C. H. Huang, S. B. Chen, and A. Chin,” La2O3 and Si0.3Ge0.7 p-MOSFETs with high hole mobility and good device characteristics,” IEEE Electron Device Lett., vol. 23, no. 12, pp.710-712, December 2002.
[28] M. Depas, T. Nigam, and M. M. Heyns, “Soft breakdown of ultra thin gate oxide layers,” IEEE Trans. Electron Devices, vol. 43, no. 9, pp. 1499-1503, 1996.
[29] E. Rosenbaum, J. C. King, and C-M Hu, “Accelerated testing of SiO2 reliability,” IEEE Trans. Electron Devices, vol. 43, no. 1, pp. 70-80, 1996.
[30] I. C. Chen, S. E. Holland, and C. Hu, “Electron-trap generation by recombination of electrons and holes in SiO2,” J. Appl. Phys., vol. 61, pp. 4544-4548, 1987.
[31] I. C. Chen, S. E. Holland, and C. Hu, “Oxide breakdown dependence on thickness and hole current-enhanced reliability of ultra-thin oxides,” Int. Electron Devices Meet., p. 660, 1986.
[32] N. Zhan, K. L. Ng, M. C. Poon, H. Wong, and C. W. Kok, ”Charge trapping and stress-induced dielectric breakdown characteristics of HfO2 films,” Electron Devices and Solid-State Circuits, 2003 IEEE Conference on 16-18, pp. 369-372, December 2003.
[33] Y. H. Kim, K. Onishi, C. S. Kang, H. J. Cho, R. Choi, S. Krishnan, M. S. Akbar, and J. C. Lee,” Thickness dependence of Weibull slopes of HfO2 gate dielectrics,” IEEE Electron Device Lett., vol 24, no. 1, pp. 40-42, January 2003.
[34] Y. H. Kim, K. Onishi, C. S. Kang, H. J. Cho, R. Nieh, S. Gopalan, R. Choi, J. Han, S.Krishnan, and J. C. Lee, ”Area dependence of TDDB characteristics for HfO2 gate dielectrics,” IEEE Electron Device Lett., vol 23, no. 10, pp. 594-569, October 2002.
[35] T. Nigam, R. Degraeve, G. Groeseneken, M. M. Heyns, and H. E. Maes, “Constant current charge-to-breakdown: Still a valid tool to study the reliability of MOS structures?,” in Proc. IRPS, pp. 62-69, 1998.
[36] I. C. Chen, S. E. Holland, and C. Hu, “Electrical breakdown in thin gate and tunneling oxides,” IEEE Trans. Electron Devices, vol. 32, pp. 413–422, February 1985.
[37] J. C. Lee, I. C. Chen, and C. Hu, “Modeling and characterization of gate oxide reliability,” IEEE Trans. Electron Devices, vol. 35, no. 12, pp. 2268–2278, December 1988.
[38] J. Prendergast, J. Suehle, P. Chaparala, E. Murphy, and M. Stephenson, “TDDB characterization of thin SiO2 films with bimodal failure populations,” in Proc. IEEE IRPS, 1995, pp. 124-130.
[39] J. W. McPherson, and D. A. Baglee, “Acceleration factors for thin gate oxide stressing,” in Proc. IEEE IRPS, 1985, pp. 1-5.
[40] L. Kang, B. H. Lee, W. J. Qi, Y. Jeon, R. Nieh, S. Gopalan, K. Onishi, and J. C. Lee, ”Electrical characteristics of highly reliable ultrathin hafnium oxide gate dielectric,” IEEE Electron Device Let., vol 21, no. 4, pp. 181-183, April 2000.
[41] S. J. Lee, S. J. Rhee, R. Clark, and D. L. Kwong, ”Reliability projection and polarity dependence of TDDB for ultra thin CVD HfO2 gate dielectrics,” VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on 11-13, pp. 78-79, June, 2002.
[42] K. Onishi, C. S. Kang, R. Choi, H. J. Cho, S. Gopalan, R. Nieh, S. Krishnan, and J. C. Lee, ”Charging effects on reliability of HfO2 devices with polysilicon gate electrode,” Reliability Physics Symposium Proceedings, 2002. 40th Annual 7-11, pp. 419-420, April 2002.
[43] B. H. Lee, L. Kang, W. J. Qi, R. Nieh, Y. Jeon, K. Onishi, and J. C. Lee,
”Ultrathin hafnium oxide with low leakage and excellent reliability for alternative gate dielectric application,” Electron Devices Meeting, IEDM Technical Digest. International 5-8, pp. 133-136, December 1999.
[44] Y. H. Kim, K. Onishi, C. S. Kang, R. Choi, H. J. Cho, R. Nieh, J. Han, S. Krishnan, A. Shahriar, and J. C. Lee, ”Hard and soft-breakdown characteristics of ultra-thin HfO2 under dynamic and constant voltage stress,” Electron Devices Meeting, IEDM Digest. International 8-11, pp. 629-632, December 2002.