這篇論文提出了第一個自動化且同時生成時脈精準以及時脈數精準的交易層級匯流排模型的方法。當交易層級模型建立被證實為一個有效管理系統層級設計複雜度的方法，研究者們往往利用不同層級的（交易層級）模型達到快速或準確的系統層級模擬。如此一來，設計者往往花費大量的時間在重新建立相同的模型在不同的抽象層級上，費時且容易犯錯，更難以確保其不同抽象層級模型的一致性。這篇論文提出了一個自動化的方法，同時生成快與準的兩種抽象層級，幫助設計者除去易錯且費時的模型建立及確認一致性的工作。

This paper proposes the first automatic approach to simultaneously generate Cycle Accurate and Cycle Count Accurate transaction level bus models. As TLM (Transaction Level Modeling) is proven an effective design methodology to manage ever-increasing complexity of system level designs, researchers often exploit various abstraction levels to gain either simulation speed or accuracy. Consequently, designers time and again wearily re-write and perform consistency check for different abstraction level models of the same design. To ease the work, we propose a novel correct-by-construction method that automatically and simultaneously generates multiple transaction level bus models for system simulation that can be both fast and accurate. The proposed approach relieves designers from tedious work for model refinement and error-prone consistency check.

[1] T. Grötker, S. Liao, G. Martin, S. Swan, System Design with SystemC, Kluwer Academic Publishers, 2002.
[2] D. Gajski, J. Zhu, R. Domer, A. Gerstlaner, and S. Zhao, SpecC: Specification Language and Methodology, Kluwer Academic Publishers, 2000.
[3] S. Malik, X. Zhu, "A hierarchical modeling framework for on-chip communication architectures", Proc. Computer-Aided Design, 2002, pp. 663-671.
[4] O. Ogawa, et al., "A practical approach for bus architecture optimization at transaction level", Design, Automation and Test in Europe Conf., 2003, pp. 176-181.
[5] M. Caldari, et al., "Transaction-level models for AMBA bus architecture using SystemC 2.0", Design, Automation and Test in Europe Conf., 2003, pp. 26-31.
[6] A. Harverinen, M. Leclercq, N. Weyrich, D. Wingard, “A SystemC™ OCP Transaction Level Communication Channel”, Technical Report’07.
[7] W. Klingauf, R. Günzel, O. Bringmann, P. Parfuntseu, and M. Burton, "GreenBus: a generic interconnect fabric for transaction level modeling ", Proc. Design Automation Conf., 2006, pp. 905-910.
[8] S. Pasricha, N. Dutt, M. Ben-Romdhane, "Extending the Transaction Level Modeling Approach for Fast Communication Architecture Exploration", Proc. Design Automation Conf., 2004, pp. 113-118.
[9] Open SystemC Initiative (OSCI). SystemC Version 2 Documentation.
http://www.systemc.org.
[10] D. Shin, A. Gerstlauer, J. Peng, R. Dömer, and D. Gajski, “Automatic generation of transaction level models for rapid design space exploration,” Proc. Hardware/Software Codesign and System Synthesis, 2006, pp. 64-69.
[11] S. Vercauteren, B. Lin, and H. D. Man, “Constructing Application-Specific Heterogeneous Embedded Architectures from Custom HW/SW Applications, “ Proc. Design Automation Conf., June 1996, pp. 521-526.
[12] Jon. D. Kleinsmith and D. Gajski, “Communication Synthesis for Reuse”, UC Irvine, ICS-TR-98-06, March 1998.
[13] T. Michiels, "Generating TLM bus models from formal protocol specifications", European SystemC Users Group Meeting, 2004.
[14] V. D'silva, S. Ramesh, and A. Sowmya, "Synchronous Protocol Automata: A Framework for Modeling and Verification of SoC Communication Architectures", Proc. Design, Automation and Test in Europe, 2004, pp. 20-27.
[15] Open Core Protocol International Partnership (OCP-IP), www.ocpip.org.
[16] D. Flynn. “AMBA: enabling reusable on-chip designs”, IEEE Micro, 1997, pp. 20-27.