為了系統晶片化設計(System On Chip)，高壓元件必須由傳統的垂直結構，改變為平面橫向式的設計，在本論文中，主要是以80V橫向式擴散金氧半電晶體，利用製程與電性模擬軟體進行元件的二維及三維的結構及電性模擬，探討深溝絕緣(Deep Trench Isolation, DTI)製程與高壓元件的漂移區結合時，對元件性能的影響，並最佳化設計。

In order to realize the goal of system on chip with silicon based process, the traditional vertical high-voltage device must be altered to lateral design. In this thesis, I focus on the design of 80 volt high-voltage LDMOS device by using Technology Computer-Aided Design tool for two- dimension and three- dimension simulation on electrical properties. And analyzed the device performance of the combined deep trench isolation process and the drift region in high voltage applications. The design is optimized and the simulation results are discussed.

[1] B.JAYANT BALIGA, ”POWER SEMICONDUCTOR DEVICE,”PWS PUBLISHING COMPANY, 1996
[2] J. Ramos and M. Steyaert, “STI/LOCOS compatible LDMOS structure in standard CMOS,” ELECTRONICS LETTERS 18th September 2003 Vol. 39 No. 19
[3] A. Nezar and C. A. T. Salama, Fellow, IEEE, “Breakdown Voltage in LDMOS Transistors Using Intemal Field Rings,” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 38, NO. 7. JULY 1991
[4] Zia Hossain, Mohamed Imam, Joe Fulton, M a s h Tanaka, “Double-resurf 700V N-channel LDMOS with Best-in-class On-resistance,” 0-7803-731 &9/02/2002 IEEE
[5] Zia Hossain, “Determination of Manufacturing Resurf Process Window for a Robust 700V Double Resurf LDMOS Transistor,” Proceedings of the 20th International Symposium on Power Semiconductor Devices & IC's May 18-22, 2008 Oralando, FL
[6] C. T. Huang1,2, Bing-Yue Tsui1, Hsu-Ju Liu1, and Geeng-Lih Lin3, “The Impact of High-voltage Drift N-well and Shallow Trench Isolation Layouts on Electrical Characteristics of LDMOSFETs,” 1-4244-0637-4/07/2007 IEEE
[7] Taylor Eflantd, Peter Mei, Dan Mosher, Bob Todd, “Self-Aligned RESURF To LOCOS Region LDMOS Characterization shows Excellent Rsp vs BV Performance,” 0-7803-3 106-0/96/1996 IEEE
[8] Shinichiro Yanagi, H.Kimura, T.Nitta, T.Kuroi, K.Hatasako and S.Maegawa, “0.15μm BiC-DMOS technology with novel Stepped-STI N-channel LDMOS,” 978-1-4244-4673-5709/2009 IEEE.
[9] J.A. Appels and H.M.J. Vaes, ” HIGH VOLTAGE THIN LAYER DEVICES (RESURF DEVICES),” CH1504-0/79/0000-0238/1979 IEEE
[10] Baoxing Duan, Bo Zhang, Zhaoji Li, “A New Reduced Bulk Field (REBULF) High-Voltage LDMOS with N+-Floating Layer,” 0-7803-9584-0/06/2006 IEEE.
[11] Jianbing Cheng, Bo Zhang and Zhaoji Li, “1000 V Breakdown Voltage LDMOS with Thin Drift Layer,” 978-1-4244-2064-3/08/2008 IEEE
[12] SYNOPSYS, “Taurus Medici User Guide,” Version Y-2006.06, June 2006
[13] SYNOPSYS, “TCAD Sentaurus Training”
[14] SYNOPSYS, “TCAD Sentaurus,” Version A-2008.09
[15] SYNOPSYS, ” Taurus TSUPREM-4 Taurus Process Reference Manual,” Version X-2005.10, October 2005
[16] Martin Knaipp, Georg R□hrer, Rainer Minixhofer, and Ehrenfried Seebacher, “Investigations on the High Current Behavior of Lateral Diffused High-Voltage Transistors,” 0018-9383/04/2004 IEEE
[17] Namkyu Park, Jaehan Cha, Kyungho Lee, Haeung Jeon, Hyungsuk Choi, Juho Kim, Sungoo Kim, Inseok Oh, Eungryul Park, Jinyoung Chae, Hyunggeun Kang, Intaek Oh, HAN SUB YOON+, “aBCD18 - an advanced 0.18um BCD Technology for PMIC Application,” 978-1-4244-4673-5/09/2009 IEEE.
[18] H. Kitahara, T. Tsukihara, M. Sakai, J. Morioka*, K. Deguchi*, K. Yonemura*, T. Kikuchi**, S. Onoue**, K. Shirai*, K. Watanabe* and K. Kimura*., “A Deep Trench Isolation integrated in a 0.13um BiCD process technology for analog power ICs,” 978-1-4244-4896-8/05/2008 IEEE
[19] B. Desoete, A. De Smet, and P. Moens, “A Multiple Deep Trench Isolation Structure with Voltage Divider Biasing,” Proceedings of the 19th International Symposium on Power Semiconductor Devices & ICs May 27-30, 2007 Jeju, Korea
[20] YUAN TAUR TAK H.NING, ”Fundamentals of MODERN VLSI DEVICES,”CAMBRIDGE UNIVERSITY PRESS, 1998
[21] HU ZHI-MIN, “The optimal design of 700V LDMOSFET,” NTHU-2007.6
[22] T. Sakuda, N, Sadachika, Y. Oritsuki, M. Yokomichi, M. Miyake, T. Kajiwara, H. Kikuchihara U. Feldmann, H. J. Mattausch and M. Miura-Mattausch, ”Effect of Impact-Ionization-Generated Holes on the Breakdown Mechanism in LDMOS Devices,” 9781-4244-3949-2/09/2009 IEEE