適用於無線感測網路之動態頻率調整加解密引擎設計

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研究生：	梁蓉 Rong Liang
論文名稱：	適用於無線感測網路之動態頻率調整加解密引擎設計 A Dynamic Frequency Scaling AES Engine for Wireless Sensor Network
指導教授：	許雅三 Yarsun Hsu
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2006
畢業學年度：	94
語文別：	英文
論文頁數：	81
中文關鍵詞：	無線感測網路、動態頻率調整、AES 加解密引擎
外文關鍵詞：	Wireless Sensor Network, WSN, Dynamic Frequency Scaling, DFS, Advanced Encryption Standard, AES
相關次數：	點閱：2 下載：0
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隨著科技進步，無線通訊的發展愈加發達。在人與人的溝通之外，輔助控制的應用亦漸漸興起，無線感測網路即為其中一例。無線感測網路之應用範圍相當廣泛，從室內到室外皆有其適用之處。無線感測網路利用自我控制的小型網路來感測環境變數，並以無線方式傳輸資料，有時亦會搭配其他中央控制系統以達到隨環境變化而能自我調整之目的。

由於無線感測網路主要目的為控制、監測而非提供一個大量資訊傳輸之媒介，其網路內部節點之數量多半較為龐大，且節點之運作模式多處於閒置狀態。由於數量龐大，因此有其必要節省單一節點之面積以降低成本。另外，節點常處在閒置狀態的好處在於可以節省能源消耗，並且維持較久的壽命，因為在無線感測網路中節點通常由一個簡單的電池（或充電電池）來驅動。而除了節點成本、壽命以外，另一項需要注意的即為資料傳輸之安全性考量。

在這篇論文中，我們將討論以32位元及128位元兩種方式設計的加解密之性能，此項討論將針對面積與能源消耗兩大主軸。由討論結果可知，32位元之設計較128位元之設計節省約一半的面積且以大部分傳輸量少的無線感測網路節點而言其能源消耗亦為前者較低。由此，整體評估為32位元之設計較128位元之設計適用於無線感測網路。除此之外，我們也提供了一個適用於無線感測網路之動態頻率調整加解密引擎之系統架構，同時亦提供了此動態頻率調整加解密引擎之系統模擬結果，經由系統模擬之結果可瞭解其整體運作。

Wireless sensor network is more and more popular nowadays. Its applications are wide-spreading from household to military use. The main purpose of this kind of network is to control and monitor some parameters in the environment but not to provide an access for large amount of data transfer. Consequently, nodes in such network stay in the idle mode most of the time so they can last long with single battery as power supply. In addition to the life time of a node, the security of data transferring over the air should be concerned.

In this work, a discussion on the implementations based on 32-bit and 128-bit datapath design of the security engine will be provided. The discussion will focus on area cost down and average power consumption. From the comparison results, it is shown that the overall evaluation of the 32-bit design of the AES core prevails over the 128-bit design. Moreover, system architecture with a dynamic frequency scaling 32-bit AES core is also provided followed by a system simulation, which gives an overall function of the security engine.

Chapter 1  Introduction    1
1    Wireless Sensor Network Overview    1
2    Necessity of Security    3
3    Motivation and Objective    4
4    Thesis Organization    5
Chapter 2  Background    7
1    Advanced Encryption Standard (AES)[8]    7
1.1    AddRoundKey Transformation    10
1.2    SubBytes and InvSubBytes Transformations    11
1.3    ShiftRows and InvShiftRows Transformations    12
1.4    MixColumns and InvMixColumns Transformations    14
1.5    RoundKey Scheduling    15
2    Overview and Associated Requirements of Zigbee/IEEE 802.15.4[4]    16
2.1    Throughput Requirements    17
2.2    Security Requirements    17
Chapter 3  Implementation Results and Discussions on AES Core    20
1    Implementation of AES core    21
1.1    Key Expansion    24
1.2    AddRoundKey Transformation    25
1.3    SubBytes and InvSubBytes Transformations    25
1.4    ShiftRows and InvShiftRows Transformations    27
1.5    MixColumns and InvMixColumns Transformations    28
1.6    The Exact Block Diagram of Both Designs    34
2    Discussions on Area    34
3    Discussions on Power    36
3.1    Minimum Operating Frequency Computing    36
3.2    Power Report of Synthezied Netlists    37
3.3    Energy Consumption of A Task    38
Chapter 4  A Dynamic Frequency Scaling AES Engine for WSN    49
1    Module Overview    49
2    Clock Divider    51
3    Dynamic Frequency Wrapper    51
4    Parameter Register Bank (with AHB Slave Interface)    54
5    DMA (with AHB Master Interface)    56
6    AES Engine    59
7    Extended Connection with IEEE 802.15.4 MAC    61
8    Function of This Module    62
Chapter 5  System Simulation    64
1    EASY Platform    65
2    Simulation Data Flow    68
3    Simulation Waveform    69
Chapter 6  Conclusions and Future Works    78
1    Conclusions    78
2    Future Works    78
References    80

                                

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[11] C. P. Su, T. F. Lin, C. T. Huang, and C. W. Wu, National Tsing Hua University, A high-throughput low-cost AES processor. IEEE Communications Magazine, pp. 86-91, December 2003.
[12] V. Rijmen, Efficient implementation of the Rijndael S-box.
[13] A. Satoh, S. Morioka, K. Takano, and S. Munetoh, A compact Rijndael hardware architecture with S-Box optimization. ASIACRYPT 2001, LNCS 2248, pp. 239-254, 2001.
[14] P. Chodowiec and K. Gaj, Very compact FPGA implementation of the AES algorithm. CHES 2003, LNCS 2779, pp. 319–333, 2003.
[15] National Chip Implementation Center. http://www.cic.org.tw
[16] N. Kim, H. Lee, Design of AMBATM wrappers for multiple-clock operations. IEEE, 2004.
[17] AMBA Specification 2.0, ARM, 2001.

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