於電子封裝結構設計及製造過程中，焊錫接點可以多種方式製作，並應用於多種電子封裝結構中以做為電訊通路及結構支持，如覆晶封裝、晶圓級封裝、細節距球柵陣列封裝及晶片尺度封裝。其中焊錫接點外形預估已被視為重要之晶圓級封裝結構設計工具，以提升焊錫接點之可靠度。現今可攜式電子產品之需求正持續增長，高電性表現及低成本之晶圓級晶片尺寸封裝結構預期將成為主流之一，並主要用於記憶體元件中。然而由於晶圓級封裝並未填充底膠，當晶片尺寸較大時，如6x6平方公釐，則將遭遇可靠度不佳之問題。於傳統之晶圓級封裝結構中，焊錫接點之墊片直徑與錫球體積皆相同，此類電子元件於實際運作時，由熱負載所引致之應力/應變將集中於錫球陣列角落區域之焊錫接點上，且其位置通常較為接近晶片側。為改善晶圓級封裝結構之可靠度，本研究提出一結合解析法與能量法之混合法，用以預估封裝結構之接點於同時包含圓形及非圓形墊片之混合墊片式錫球陣列於迴焊過程中之平衡高度與幾何外形，並應用於錫球陣列設計以提升焊錫接點之疲勞壽命。於混合墊片式錫球陣列中，至少包含兩種以上之錫球體積、墊片尺寸或外形，使錫球陣列配置具有多種設計。本研究主要採用有限元素法分析軟體ANSYSâ針對晶圓級封裝結構進行加速熱循環模擬計算，以瞭解焊錫接點之應力應變行為。研究中並配合非線性及參數化有限元素法探討設計參數或項目對於封裝結構可靠度之影響。本研究並針對焊錫接點外形預估及有限元素分析方法進行實驗驗證，以確認模擬計算方法之正當性與適用性。於本研究中所探討之設計參數或項目包含焊錫接點之墊片直徑與錫球體積、晶片與應力緩衝層厚度、應力緩衝層之楊氏模數與熱膨脹係數、焊錫接點陣列配置方式等。於焊錫接點陣列配置設計方面，位於角落區域之焊錫接點可用作啞球，僅用做結構支持而無電訊導通功能，如此之設計預期將有助於分散角落區域之集中應力。除針對主要設計參數進行結構分析外，本研究亦探討設計參數之製造誤差或缺陷對於晶圓級封裝結構可靠度之影響。經由一系列之分析與探討可知，適當加大圓形墊片啞球之尺寸，或設置適當設計及方向之橢圓形墊片實球或啞球，則焊錫接點之最大等效塑性應變將顯著降低，因而可有效提升封裝結構之可靠度。此外，減小晶片厚度與增加應力緩衝層之厚度，以及採用具較低楊氏模數與較高熱膨脹係數之應力緩衝層均有助於改善焊錫接點之疲勞壽命。另一方面，若設計參數包含微量之製造誤差或缺陷，其綜合效應將顯著降低晶圓級封裝結構之可靠度。因此，設計者需經由一系列之分析與研討，以獲得較佳之晶圓級封裝結構設計，並精準控制製造誤差以確保電子元件之品質。於本研究中所獲得之分析結果經由彙整後，可做為相似之面積分佈型態電子封裝結構之設計參考，如晶片尺度封裝、覆晶封裝、細節距球柵陣列封裝等。

During the design and manufacturing processes of electronic packaging, solder joints are fabricated using a variety of methods to provide both mechanical and electrical connections for different applications such as flip-chip, wafer-level packaging, fine-pitch ball grid array (BGA), and chip-scale packaging (CSP). The solder joint shape-prediction methods have been incorporated as a design tool to enhance the reliability of the wafer-level packaging. As the demand for portable electronic equipment increases, wafer-level chip-scale-packaging (WLCSP) is expected to be widely used in static-dynamic random access memory (SDRAM) for its better electrical performance and lower manufacturing costs. However, reliability of solder joints for a large chip size such as 6mm ´ 6mm without underfill assembly is still in question. In conventional WLCSP, the dimensions of each solder ball and each solder pad are the same. The maximum thermally induced stress/strain contours occur on the die-side surface of the solder joint furthest away from the chip center. In this research, a hybrid method combining an analytical algorithm and the energy-based approach are applied to predict standoff heights and geometry profiles of the solder joints. A hybrid-pad-shape (HPS) system is also proposed to design solder ball layout and to enhance the reliability of solder joints. The HPS system contains at least two kinds of solder volume and pad size/shape as well as their relative locations during the reflow process. Next, the commercial finite-element code ANSYSâ is used to simulate the stress/strain behavior of the solder balls in WLCSP under cyclic temperature loadings. A nonlinear and parametric finite-element analysis is conducted to investigate the reliability issues that result from several design parameters. In this research, several experimental validations are completed to verify the correctness and feasibility of solder-joint shape-prediction methods and finite-element analysis procedures. The design parameters considered in this research include solder-joint layout, solder volume, pad diameter, die thickness, and thickness/material properties of the stress buffer layer (SBL). In the aspect of solder joint layout design, the solder joints located in the corner areas can be considered as structure dummy balls with no electrical signals pass through them. This research also discusses the effects of manufacturing errors of design parameters on the reliability of solder joints. The results reveal that as the WLCSP contains larger round pad or suitably oriented elliptical-pad solder joints located in the corner areas underneath the chip, the maximum equivalent plastic strain of the solder joints will be effectively reduced and the solder-joint fatigue life under thermal loading will be greatly enhanced. In addition, thinner die and thicker SBL that have lower Young’s modulus and higher CTE are also good for better reliability in the WLCSP. On the other hand, minor manufacturing errors of design parameters result in unfavorable effects on solder-joint reliability. Therefore, designers should seek the optimal design of electronic components using systematic parametric analysis and accurate control of manufacturing processes so as to ensure superior quality. Furthermore, the findings presented in this research can be used as a design guideline for electronic packaging with area-array interconnections such as CSP, flip-chip packaging, Super CSP and fine-pitch BGA.

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