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研究生: 陳志仁
Chih Jen Chen
論文名稱: 百億位元乙太網路媒體存取控制之設計與實現
Design and Implementation of 10 Gigabit Ethernet MAC
指導教授: 許雅三
Yarsun Hsu
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2004
畢業學年度: 92
語文別: 英文
論文頁數: 71
中文關鍵詞: 乙太網路媒體存取控制IC設計檢查和
外文關鍵詞: Ethernet, MAC (Media Access Control), IC design, checksum
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  • 隨著網路頻寬的需求增加,我們需要有更高速的區域網路來滿足此需求,在這篇論文中,我們設計的百億位元乙太網路正是滿足這個需求並可行的解決方案之一,由於乙太網路是目前最受歡迎的區域網路架構,所以將來我們只要將此設計直接向下相容於目前的網路架構中即可解決頻寬不足的問題,此設計是用積體電路設計的方式來實現百億位元乙太網路的媒體存取控制層,其中包含了一般媒體存取控制層的基本功能,例如:成框(framing)、定址 (addressing)、錯誤偵測等。成框是將框架(frame)之間依框架(frame)格式做分隔;定址是將媒體存取控制(MAC)位址加入框架中;錯誤偵測的功能則是利用循環冗贅核對(CRC, Cyclic Redundancy Check)來偵測框架是否發生錯誤;另外,此一設計還包含了流量控制、虛擬區域網路(Virtual LAN)以及部份框架檢查和的計算等功能。流量控制乃透過傳送一個暫停框架的方式來避免接收端的儲存空間發生滿溢;虛擬區域網路可用來減少由廣播框架所造成在頻寬上的浪費,因為交換機只將虛擬區域網路廣播框架傳遞給同一虛擬區域網路內的終端,此可減少廣播框架造成的頻寬浪費;而部份框架檢查和的計算則是對框架的資料這部份做檢查和的動作並將結果送給上層利用,這樣有助於減少傳輸層在計算檢查和時所花的處理器時間。在論文的最後,我們也對邏輯合成後的設計做分析,並驗證此設計可以達到每秒百億位元的傳輸效能。


    As the requirement of network bandwidth increases, a faster LAN (Local Area Network) protocol is needed. 10 Gigabit Ethernet is a very feasible solution to satisfy this requirement because Ethernet is the most popular one among all LAN protocols. In this thesis, an SOC (System on Chip) design flow is used to implement 10 Gigabit Ethernet MAC (Media Access Control) layer. This design implements general 10 Gigabit Ethernet MAC functions such as framing, addressing, and error detection. In addition, it also realizes a flow control scheme, the VLAN frame construction,
    and partial frame checksum computation. Flow control generates a PAUSE frame to prevent receiver buffer from overflowing. VLAN technology is helpful to reduce the
    waste of the bandwidth on broadcasting. The partial frame checksum computation can save a number of CPU cycles during the computation of TCP checksum in TCP layer.

    List of Figures List of Tables 1 Introduction.....1 1.1 Motivation and objective 1.2 Organization of this thesis 2 Background.....5 2.1 Introduction of 10GbE MAC 2.2 Main functions of 10GbE MAC 2.3 Overview of the services 2.4 MAC frame structure 2.5 Flow control 2.6 RECONCILIATION sublayer and XGMII (10 Gigabit Media Independent Interface) 2.7 Error detection with CRC-32 generator 3 Design and implementation.....18 3.1 Design environment 3.2 Global design 3.2.1 Interface introduction 3.2.2 Design modules 3.2.3 FIFO buffers introduction 3.3 Transmitter structure 3.3.1 “txr0_selector”module 3.3.2 “tx_selector”module 3.3.3 A 4-lane parallel CRC-32 generator 3.3.4 Transmit state machine 3.4 Receiver structure 3.4.1 “rx_crc_selector”module 3.4.2 CS generator module 3.4.3 Receive state machine 3.4.4 Link fault state machine 3.5 Synthesis analysis and critical solutions 3.5.1 Timing and critical path analysis 3.5.2 Area report 4 Conclusion and future work.....43 Bibliography.....45 A Simulation result.....46

    [1] 10 gigabit ethernet alliance. http://www.10gea.org/.
    [2] 802.1q. http://standards.ieee.org/getieee802/.
    [3] 802.3ae. http://standards.ieee.org/getieee802/.
    [4] CIC home page. http://www.cic.edu.tw.
    [5] IEEE p802.3ae 10gb/s ethernet task force.
    http://grouper.ieee.org/groups/802/3/ae/.
    [6] PCI express homepage. http://www.pcisig.com/home.
    [7] G. Patane G.Campobello and M. Russo. Parallel CRC realization. IEEE TRANSACTIONS ON COMPUTERS, 52, 2003.
    [8] T. Henriksson and D. Liu. Implementation of fast CRC calculation. Design Automation Conference, 2003, Proceedings of the ASP-DAC 2003. Asia and South
    Paci…c, pages 563–564, 2003.
    [9] J. H. Huang and C. W. Chen. On performance measurements of TCP/IP and its device driver. Local Computer Networks, 1992. Proceedings., 17th Conference on, 13-16:568 –575, 1992.
    [10] J.Touch and B. Parham. Implementing the internet checksum in hardware. Network working Group, 1996.
    [11] J. Kay and J. Pasquale. Pro…ling and reducing processing overheads in TCP/IP. Networking, IEEE/ACM Transactions on, 4:817 –828, 1996.

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