對於使用深度網路來進行微影成像預測的學習模型，事實上，要模擬微影成像過程中從最初積體電路設計到最終晶圓產出的電路之間的非線性的輪廓變換是非常困難且複雜的。這類微影模擬所採用的深度學習模型，其效果及表現通常受到成對的訓練資料所影響，每筆成對的訓練資料會由一張固定圖片大小的積體電路設計，以及其對應到的最終製程產出的拍攝影像。然而，針對不同設計的積體電路樣式，我們需要透過蒐集新晉資料分布的訓練資料來更新我們現有的預訓練模型，而蒐集製程產出的拍攝影像，是需要投入大量時間以及大量金錢去進行真實的半導體製程的。因此，我們應用深度網路的學習模型，提出了基於自我關注的全局和局部圖形的新穎分數來對積體電路設計進行新穎偵測。這種方法透過選出對於預訓練模型而言，能夠挾帶更多新穎資訊以及為模型帶來成長價值的訓練資料，亦能作為主動學習的預先挑選程序。
基於殘差網路和分類模型上近年的新穎偵測作法，我們設計的積體電路新穎偵測模型是由兩個子網路架構所組成：一個用於為積體電路的全體佈局相似度所評分的自動編碼器，和一個用於偵測局部輪廓變換差異所使用預訓練模型中的前段編碼器。將新晉的設計和原先的訓練資料分布進行比對，來進行新穎偵測。而基於原先設計的預訓練深度網路模型，我們更透過套用的自監督學習的模塊進行微調，來讓原先基於局部的判斷的子網路可以容納更為廣範圍的資訊。且我們所提出的方法可以只透過觀測積體電路設計就能預測微影成像中輪廓變化的新穎程度，而不需要提前經過製程上需求的大量時間和金錢花費。在後續的實驗部分也能證明我的積體電路的新穎偵測算法的有效性。

The fact that it is too complicated to model the non-linear shape distortion of the fabrication result of a designed IC pattern urges the development of learning-based pre-simulation models. Such models are usually driven by pairwise training samples, each consisting of a layout pattern and a reference contour image after one certain fabrication step.
However, it is expensive and time-consuming to collect reference contour images of layouts for training and fine-tuning such pre-simulation models via the IC fabrication process.
Therefore, we propose a deep learning-based layout novelty detection algorithm with a SA-Glocal (self-attention global-local) novelty score. The proposed algorithm can act as an active learning oracle, based on which users can find a reduced amount of layouts worthy enough to be fabricated for acquiring the ground-truth circuit contours of their IC products.
Inspired by residual-based and classification-based novelty detection models,
we also devise a layout novelty detection method that can assess the potential novelty of a layout by exploiting two subnetworks, an auto-encoder and a pretrained layout-to-SEM prediction model. The former subnetwork characterizes the global structural similarity between the given layout and training samples, and the latter can derive an attention-guided latent code depicting the local deformation.
Through this design, the proposed method can be deployed in the absence of ground-truth circuit contours.
Experimental results demonstrate that the proposed method can detect novel layout patterns effectively.

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