技術演進(technology migration)在產品週期中扮演很重要的角色，比較被關注的項目為layout compaction 的重新使用和硬體程式語言的重新使用，但有關flip-chip的繞線卻乏人問津。錫球(bumps)的個數也隨著技術演進的腳步逐漸減少，因此在flip-chip上做RDL 繞線的問題越來越複雜。這篇論文是在解決在錫球(bumps)個數有限的情況下，如何在最短線長的目標下進行RDL 繞線，我們所採用的方法是minimum cost maximum flow 演算法，實驗結果顯示我們的方法可以比maze routing的方法線長減少約69%

Technology migration plays a critical role in the time-to-market competition. Most existing works focus on layout compaction or hardware description language re-synthesis, and pay little attention to the I/O interface in flip chips. The complication of bumping process as well as electrical and reliability considerations prevent the bumps from scaling with transistor sizes. On the other hand, the number of signal bumps cannot be reduced and sometimes even increases due to the demands for wider bandwidth and various peripheral devices. As a result, the allocated die area for I/O can no longer afford the number of bumps a chip requires. This issue, known as bump encroachment, puts a stringent requirement on the redistribution layer (RDL) routing. In this paper, we first formulate the problem of RDL routing with bump encroachment, and then propose a network flow based algorithm to efficiently address it. Experimental results on a few benchmarks with parameters extracted from industrial designs show that compared with a maze routing-based approach, our algorithm can achieve up to 69% wirelength reduction.

[1] R. Nitzan and S. Wimer, “AMPS and SiClone integration for implementing 0.18 um to 0.13 um design migration,” in Proc. of the Synoposys Users Group (SNUG) Conference, San Jose CA, March, 2002.
[2] http://www.intel.com/content/www/us/en/silicon-innovations/intel-tick-tock-model-general.html
[3] R. Saleh et al, “System-on-chip: reuse and integration,” in Proc of IEEE 94(6): 1050–1069, 2006
[4] S-Y. Chiang, “Foundries and the dawn of an open IP era,” Computer 34(4): 43–46, 2001
[5] T. Lengauer, “Compaction. In: Combinatorial algorithms for integrated circuit layout,” Wiley, Chichester, pp 579–643, 1990
[6] M. Reinhardt, “Automatic layout modification: including design reuse of the alpha cpu in 0.13 micron soi technology,” Kluwer, Norwell, MA, 2002
[7] E. Shaphir, R. Y. Pinter and S. Wimer, “Efficient cell-based migration of VLSI layout,” Springer, US, 2014
[8] S. Wimer, “Planar CMOS to multi-gate layout conversion for maximal fin utilization,” Integration, 47:115–122, 2014
[9] De Vos, J.; Bogaerts, L.; Buisson, T.; Gerets, C.; Jamieson, G.; Vandersmissen, K.; La Manna, A.; Beyne, E., "Key elements for sub-50μm pitch micro bump processes," Electronic Components and Technology Conference (ECTC), 2013 IEEE 63rd , pp.1122-1126, 2013
[10] W. Zhang, Z. Mai, L. Bogaerts, M. Gonzalez, G. Vakanas; A. La. Manna, E. Beyne, "Mechanical characterization of micro-bump for aggressive bump scaling," Electronic System-Integration Technology Conference (ESTC), 2012 4th, pp.1-5, 2012
[11] http://www.itrs.net
[12] Hsu-Chieh Leey, Yao-Wen Chang, and Po-Wei Lee, “Recent Research Development in Flip-Chip Routing,” Proc. ICCAD, 2010.
[13] Jia-Wei Fang, Martin D. F. Wong, and Yao-Wen Chang,“Flip-Chip Routing with Unified Area-I/O Pad Assignments for Package-Board Co-Design” Proc. DAC, 2009.
[14] X. Liu, Y. Zhang, G. K. Yeap, C. Chu, J. Sun, and X. Zeng, “Global routing and track assignment for flip-chip designs,” Proc. DAC, pp. 90–93, 2010.
[15] J.-W. Fang, C.-H. Hsu, and Y.-W. Chang, “An integer linear programming based routing algorithm for flip-chip design,” Proc. of DAC, pp. 606–611, 2007.
[16] P.-W. Lee, C.-W. Lin, and Y.-W. Chang, “An efficient pre-assignment routing algorithm for flip-chip designs,” Proc. ICCAD, pp. 239–244, 2009.
[17] J.-T. Yan and Z.-W. Chen, “RDL pre-assignment routing for flip-chip designs,” Proc. GLSVLSI, pp. 401–404, 2009.
[18] J.-W. Fang, K.-H. Ho, and Y.-W. Chang, “Routing for chip-package-board co-design considering differential pairs,” Proc. ICCAD, 2008.
[19] J.-T. Yan and Z.-W. Chen, “IO connection assignment and RDL routing for flip-chip designs,” Proc. ASP-DAC. pp. 588–593, 2009
[20] J.-W. Fang, I-J. Lin, P.-H. Yuh, Y.-W. Chang, and J.-H. Wang, “A routing algorithm for flip-chip design,” Proc. ICCAD, pp.“A routing algorithm for flip-chip design,” Proc. ICCAD, p 753-758,2005
[21] CS2. min cost flow solver. [Online]. Available: http://www.igsystems.com
[22] R.J. Vanderbei, Linear Programming: Foundations and Extensions. New York: Springer, 2007