研究生: |
張其聖 Chi-Sheng Chang |
---|---|
論文名稱: |
半導體產業研發設計階段以WAT參數資料建構黃金晶方分析模型 Building the Golden Die Analytical Model at R&D Stage with WAT Parameters in Semiconductor Manufacturing |
指導教授: |
陳飛龍
劉淑範 |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
工學院 - 工業工程與工程管理學系 Department of Industrial Engineering and Engineering Management |
論文出版年: | 2008 |
畢業學年度: | 96 |
語文別: | 中文 |
論文頁數: | 99 |
中文關鍵詞: | 半導體 、相關係數矩陣 、晶圓允收測試 、類神經網路 、黃金晶方 |
外文關鍵詞: | Semiconductor, Correlation Matrix, Wafer Acceptance Test, Artificial Neural Network, Golden Die |
相關次數: | 點閱:3 下載:0 |
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在這個資訊爆炸的時代,隨著電子科技以及網際網路科技的進步,致使全球電子市場消費水準的提升,帶動了半導體產業的蓬勃發展。對於半導體製造業而言,複雜的晶圓製程、昂貴的原材料以及嚴格的生產環境等等因素,造成居高不下的生產成本。因此,各大晶圓廠莫不急於藉由各種製程控制與分析手法,以求能夠降低成本並提高良率,進而使最終獲利量能夠提升。然而,對於現今之半導體研發設計階段而言,為求能夠達到具體客觀的分析,通常均針對晶圓上之WAT參數部分採取全測的方式進行;但由於該階段屬於測試性製程,所產生之WAT參數往往高達千百項以上,因此相當地耗費人力資源及成本。故若能藉由蒐集而得之WAT資料做研究,建構發展出一套適用於該階段之分析模型,對於節省成本以及提升良率將會有莫大的幫助。有鑒於此,本研究將於此塊領域著手進行,針對研發設計製程之WAT參數進行分析,冀能從中找出整片晶圓以及群聚中的黃金晶方(Golden Die),提供相關半導體廠作為參考的指標。本研究進行的步驟,首先採用相關係數矩陣以及品質管制圖等分析手法,針對原始WAT資料做前置處理,以選取出獨立且具有代表性的晶方,然後利用類神經網路中的自組織映射網路(SOM)進行樣本訓練,依特徵將選取過後之晶方的WAT參數進行分群;最後則針對各群聚內WAT參數的部份,利用群聚分析中之城市街道距離衡量手法,找出各群聚內具代表性之黃金晶方。經由系統實作結果發現可將WAT參數資料分為九群,並能找出整體以及各群聚內3、13之代表性黃金晶方,足提供該階段產線研發工程師日後晶圓電路設計的參考依據,而達成本研究之目標。
For semiconductor manufacturing industries, they usually have formed very high production costs because of the complicated manufacturing process of the manufacturing environment and expensive equipments. Almost every semiconductor company expects to reduce costs and enhance yield by applying the relative analytical techniques for its complex manufacturing steps. However, at the R&D stage of semiconductor fabrication, they always test the whole dies of one wafer in order to reach the highest accuracy. That is extremely time-consuming and labor intensive because of thousands of hundreds WAT parameters produced at the stage. Thus, it would be very beneficial to reduce costs if we can develop an analytical model suitable for this stage based on the relative WAT collecting data. This paper proposed an analytical model to find the “Golden Dies” of the relative wafer with WAT data at the R&D stage of semiconductor fabrication. The analytical model consists of three steps. First, the correlation matrix and the QC chart are utilized to reduce dimensions of raw WAT data collected from EDA to determine the representative dies of the wafer. The second step uses a known neural network architecture known as SOM to generate clusters within it. At final step, City-Block Distance Measure is applied to find out the golden dies of each cluster. Experimental results show that the proposed methodology can classify all dies into nine groups and successfully find out the golden dies.
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