簡易檢索 / 詳目顯示

研究生: 涂漢威
Dennis Tu
論文名稱: 晶圓製造廠考慮等候時間限制之批量放行法則
Lot Permission Rule in Wafer Fabrication Factories with Queue-Time-Limit Considerations
指導教授: 洪一峰
Yi Feng Hung
口試委員:
學位類別: 碩士
Master
系所名稱: 工學院 - 工業工程與工程管理學系
Department of Industrial Engineering and Engineering Management
論文出版年: 2005
畢業學年度: 93
語文別: 中文
論文頁數: 40
中文關鍵詞: 晶圓製造重工批量放行模擬
外文關鍵詞: wafer fabrication, rework, lot permission, simulation
相關次數: 點閱:2下載:0
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • 對於半導體晶圓製造而言,影響產出量及良率的因素有很多,其中之一便是等候時間限制。在特定製程間會有等候時間之限制,前製程完成後需於特定等候時間限制內進入後製程,超過此一時限會產生品質問題,需進行重工損耗產能。但是晶圓生產所具有的加工特性,如批量加工、重工、回流、等候時間限制、及漫長的生產週期,都增加了生產管理的複雜度,這使得發展一套方法來減少重工並提高產出變得相當困難。如果一個批量在來到特定的製程段前端,能事先預知此批量進行加工後是否會超過等候時間限制,則可避免重工及報廢的發生,減少產能的浪費而提高產出。有鑑於此,有必要發展一套在此複雜的環境中,能提高產量的批量放行法則。
    本論文針對半導體生產製程中的某段製程,加工步驟與步驟間具有等候時間限制,在多產品、多途程、多工作站、平行加工機台的環境,且具有重工及回流的特性下,提出以模擬為基礎的批量放行法則,目的在預防晶圓在加工過程中,因超過等候時間限制所造成重工或報廢,除了能節省生產成本,也提高了良率和產出量。
    經過模擬實驗的結果分析,發現以模擬為基礎的批量放行法,在不同的環境設置下,均比先進先出法,更能提高產量。從此結果可知以模擬為基礎的批量放行法,在具有等候時間限制下,對於產出具有一定的效益。


    As far as the wafer fabrication process is concerned, there are many factors affecting the throughput and yield rate. One of them is the “Queue-Time-Limit”. Certain process steps have the queue-time-limit, which means a lot needs to begin the following process step within certain time limit after it completes its operation of the previous process step. If a lot exceeds the queue-time-limit, quality issues will occur and the lot needs to be reworked. This will waste the machine capacity. The characteristics of the wafer fabrication process, like rework, re-entrant, queue-time-limit, and long production cycle time, make the production management difficult. If a lot arrives for a certain process step, the manager can prevent the lot from rework if he can foresee whether the lot will exceed queue-time-limit or not in advance. Once the rework can be reduced, the throughput of the fab will be increased. Therefore, it is necessary to develop a lot permission rule to determine whether a lot should go or not in advance in this complicated production environment.
    This research focuses on certain process steps having the queue-time-limit between some steps of the whole wafer production steps,. We propose a methodology called simulation-based lot permission rule (SBLP) in a multi-product, multi-route, multi-workstation, multi-machine environment with rework and re-entrant features. The purpose of SBLP is to prevent the lot from rework, saving the capacities of machines, thus to increase throughput.
    After simulation experiments, the results show that SBLP outruns FCFS in many environment settings like different demand-to-capacity ratios and different queue-time-limit levels. Therefore, we conclude that SBLP has significant effects on throughput.

    目錄 I 圖目錄 III 表目錄 IV 第一章 前言 1 1.1研究背景與動機 1 1.2 研究目的 3 1.3 研究範圍與限制 4 1.4 研究步驟與架構 5 第二章 文獻回顧 7 2.1半導體製造系統簡介 7 2.1.1 半導體製造相關名詞定義 7 2.1.2 半導體製造程序簡介 8 2.2派工法則回顧 12 2.3 投料法則回顧 14 第三章 研究方法 19 3.1 問題描述 19 3.2 等候時間限制 19 3.3 以模擬為基礎的批量放行法則 21 3.3.1 簡介 21 3.3.2 決策邏輯 22 第4章 模擬實驗 25 4.1 模擬中的模擬 25 4.2 模擬建構 26 4.2.1 事件排程法 26 4.2.2 模擬程式參數設定 27 4.2.3 實驗因子與架構 28 4.3 實驗結果 30 4.3.1 等候時間限制水準不同 30 4.3.2 需求/產能比不同 31 第5章 結論與未來研究方向 33 5.1 結論 33 5.2 未來研究方向 34 參考文獻 35

    Alexander K. Schömig and Matthias Kahnt (1995), “Performance modelling of pull manufacturing systems with batch servers”, Emerging Technologies and Factory Automation, ETFA. INRIA/IEEE Symposium, Vol. 3, pp. 175−183.
    Bauer, A., R. Bowden, J. Browne, J. Duggan and G. Lyous (1991), Shop Floor Control Systems, Chapman & Hall
    Fowler, J. W., Phillips, D. T., and Hogg, G. Lyous (1992), “Real-Time Control of Multi-Product Bulk-Service Semiconductor Manufacturing Process”, IEEE Transactions on Semiconductor Manufacturing, Vol. 5, No. 2, pp. 158-163.
    Glassey, C. R., and M.G.C., Resende (1988), “Closed-loop Job Shop Release Control for VLSI Circuit Manufacturing”, IEEE Transaction on Semiconductor Manufacturing, Vol.1, No.1, pp. 26- 46.
    Glassey, C. R. and Weng, W. W. (1991), “Dynamic Batching Heuristic for Simultaneous Processing”, IEEE Transactions on Semiconductor Manufacturing, Vol. 4, No. 2 pp. 77-82.
    Jaeger, R. C. (1989), Modular Series on Solid State Devices, Vol. V – Introduction to Microelectronic Fabrication, Addison-Wesley Co..
    Lozinski, C. and Glassey, C. R. (1988), “Bottleneck Starvation Indicators for Shop Floor Control”, IEEE Transactions on Semiconductor Manufacturing, Vol. 1, No. 4, pp. 147-153.
    Leachman, R. C. Solorzano, M. and Glassey, C. R. (1988), A Queue Management Policy for the Release of Factory Work Orders, ORC report, University of California, Berkeley.
    Lou, S. and Kager, P. W. (1989), “A Robust Production Control Policy for VLSI Wafer Fabrication,” IEEE Transactions on Semiconductor Manufacturing, Vol. 2, No. 4, pp. 159-164.
    Lou, S., Yan, H., Sethi, S., Gardel, A., and Deosthali, P. (1991), Using Simulation to Test the Robustness of Various Existing Production Control Policies, Proceedings of the 1991 Winter Simulation Conference, pp. 261-269.
    Neuts, M. F. (1967), “A General Class of Bulk Queues with Poisson Input,” Annals of Mathematical Statistics, Vol. 38, No. 3, pp. 759-770.
    Runyan, W. R. and K. E. Bean (1990), Semiconductor Integrated Circuit Processing Technology, Addison-Wesley Co..
    Robinson, J. K., Fowler, J. W., and Bard, J. F. (1995), “The Use of Upstream and Downstream Information in Scheduling Semiconductor Batch Operations”, International Journal of Operation Research, Vol. 33, No. 7, pp. 1849-1869.
    Spearman, M. L., Woodruff, D. L., and Hopp, W. J. (1990), “CONWIP: a Pull Alternative to Kanban,” International Journal of Production Research, Vol. 28, No. 5, pp. 879-894.
    Schragenheim E., and B., Ronen (1990), “Buffer Management :A Diagnostic Tool forProduction Control”, Production and Inventory Management Journal, Third Quarter, pp.74- 79.
    Vig, M. M. and Dooley, K. J. (1991), “Dynamic Rules for Due-Date Assignment,” International Journal of Production Research, Vol. 29, No. 7, pp. 1361-1377.
    Van Der Zee, D. J., Van Harten, A., and Schuur, P. C. (1997), “Dynamic Job Assignment Heuristics for Mulit-Server Batch Operations--A cost based approach,” International Journal of Production Research, Vol. 35, No. 11, pp. 3063-3093.
    Wein, L. M. (1988), “Scheduling Semiconductor Wafer Fabrication,” IEEE Transactions on Semiconductor Manufacturing, Vol. 1, No. 3, pp. 115-130.
    Weng, W. W. and Leachman, R. C. (1993), “An Improved Methodology for Real-Time Production Decisions at Batch-Process Work Stations,” IEEE Transactions on Semiconductor Manufacturing, Vol. 6, No. 3, pp. 219-225.
    Yan, H., Lou, S., Sethi, S., Gardel, A., and Deosthali P. (1996), “Testing the Robustnesss of Various Production Control Policies in Semiconductor Manufacturing”, IEEE Transactions on Semiconductor Manufacturing, Vol.9, No. 2, pp.285- 289.
    大野耐一 (1981), 豐田生產方式與現場管理, 日本能率協會中華企業管理發展中心
    莊達人 (1997), VLSI 製造技術, 高立圖書有限公司
    莊建鏵 (2003), 基於等候時間分配的達交率導向派工法則, 清華大學工業工程研究所碩士論文
    洪一峰, 陳守忠 (1999), “利用等候線管理之半導體製造投片控制”, 管理與系統, Vol. 6, No. 1, pp. 93-110
    蔡啟聰 (1996), 晶圓製造廠考慮等候時間限制之派工策略, 交通大學工業工程研究所碩士論文

    無法下載圖示 全文公開日期 本全文未授權公開 (校內網路)
    全文公開日期 本全文未授權公開 (校外網路)

    QR CODE