近幾年來，電力的消耗已經成為在設計電路時，一個主要的考量因素了。如何在維持相同效率之前，減少電力的消耗呢？前人有許多的研究在著重在於如何使用“縮小邏輯閘”（Down Sizing）這項技術來節省動態電力（Dynamic Power）的消耗，或是使用“臨界電壓加大”(High threshold voltage assignment)這項技術來節省靜態電力(Leakage Power)的消耗。

　　我們知道，減少電力的消耗可以分成二個部分，
1. 活動模式（Active mode）下的電力：
□ 動態電力
□ 靜態電力
2. 閒置模式（Idle mode）下的電力
□ 靜態電力

我們發現，決定要使用“改變邏輯閘大小”或“改變臨界電壓”的時候，邏輯閘開關的機率（switching density）是一個很重要的指標。如果想要使電路的效能變佳，對於那些經常在開關的邏輯閘，就要使用“臨界電壓變小”，而很少在開關的邏輯閘，就要使用“加大邏輯閘”。如果想要節省電力消耗，對於那些經常在開關的邏輯閘，就要使用“縮小邏輯閘”，而很少在開關的邏輯閘，就要使用“降低臨界電壓”。

我們設計了一套演算法，由邏輯閘開關的機率為出發點，利用“改變邏輯閘大小”及“改變臨界電壓”這二種方法來減少電力的消耗。由實驗結果可得知，使用我們的方法，在活動模式占100%、 50% 和10%的情況之下，可節省16.26%、18.53%、26.70%的電力消耗。

Power consumption has become one of the most important design considerations in circuit design recently. One design problem is modelled as "Under a timing constraint, minimize power as much as possible". Previous research focused on either minimizing the dynamic power by down sizing nodes on non-critical paths to utilize their timing slack, or reducing leakage power consumption by dual threshold assignment by using high-Vth gates on
the non-critical path. However, given a timing constraint, to minimize total power consumption including active mode (dynamic and leakage power) and idle mode (leakage power), optimization algorithm must be able to utilize sizing and threshold voltage assignment two techniques interchangeable to obtain the best gain. We ‾nd that switching activity of a gate plays an important role in making decision as to choosing gate sizing or threshold assignment. For high switching density gates, Vth assignment should be used
while for low switching density gates, gate sizing should be utilized. We develop an algorithm to perform ggate sizing and Vth assignment simulta-neously taking switching activity into consideration. The results show that
under the same timing constraint, our method can achieve 16.26%, 18.53%, and 26.70% improvement as compared the original circuits while the fraction of active time are 100%, 50%, and 10%.

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