在多核心處理器的運作下，對於記憶體的頻寬需求量也隨之提高。所以透過矽穿孔堆疊動態隨機存取的記憶體能夠滿足高頻寬的需求。然而，這堆疊的結果會導致功率密度提高，連帶產生高溫散熱的問題，舉凡資料的可靠度、記憶體效能以及額外必須負擔的冷卻成本。除了散熱的問題，在多核心的環境下，程序間的記憶體干擾亦會有損系統效能。為了達到最佳的效能，我們提出動態考量散熱與存取模式的配置方法，方法中考慮到資料的使用頻率、各層的位置分佈、散熱影響、頻寬變化量、記憶體干擾。我們利用數學分析模型估算系統效能，並考量到上述的所有影響因素。實驗結果顯示，我們提出的記憶體配置方法效能上比起傳統配置方法快12.7%。此外，我們的數學分析模型平均錯誤比率只有0.86%。

Three-dimensional (3-D) memory stacking like Hybrid Memory Cube (HMC) can resolve
memory bandwidth challenges for multi-core system where stacked multiple DRAM dies are
connected by Through Silicon Vias (TSVs). However, high power density due to the high in-
tegration incurs temperature related problems in reliability, performance, and system cooling
cost. In addition to thermal issues, in multi-core system, memory interference between pro-
cesses may degrade system performance. In order to achieve better performance, we propose
a dynamic page allocation policy considering access frequency of pages, physical locations of
DRAM dies, thermal impacts, bandwidth variation of each process, and memory interference
among processes. We also propose an analytical model to estimate the system performance
considering the above factors. Experimental results show that our proposed memory mapping
policy can outperform MCP [1] 12.7% on average. The average error rate of our analytical
model is only 0.86%.

[1] O. Mutlu M. Kandemir Thomas Moscibroda S. P. Muralidhara, L. Subramanian. Re-
ducing memory interference in multicore systems via application-aware memory channel
partitioning. In MICRO'11, pages 374-385, 2011.
[2] Wm. A. Wulf and Sally A. McKee. Hitting the memory wall: Implications of the
obvious. In ACM SIGARCH Computer Architecture News, pages 20-24, 1995.
[3] J. Jeddeloh and B. Keeth. Hybrid memory cube new dram architecture increases density
and performance. In VLSI Technology (VLSIT), 2012 Symposium, pages 87-88, 2012.
[4] B. Black, D. W. Nelson, C. Webb, and N. Samra. 3d processing technology and its
impact on ia32 microprocessors. In Proceedings of ICCD, pages 316-318, 2004.
[5] K. Banerjee, A. Mehrotra, A. Sangiovanni-Vincentelli, and Hu Chenming. Thermal
eects in deep submicron vlsi interconnects. In Design Automation Conference (DAC),
pages 885-891, 1999.
[6] S. Zhang and Z. Zhu. Access-aware memory thermal management. In IEEE Inter-
national Conference on Networking, Architecture and Storage (NAS), pages 268-274,
2014.
[7] M. J. Khurshid and M. Lipasti. Data compression for thermal mitigation in the hybrid
memory cube. In ICCD'13, pages 185-192, 2013.
28
[8] A.-C. Hsieh and T.-T. Hwang. Thermal-aware memory mapping in 3d designs. In
DATE'09, pages 1361-1366, 2009.
[9] J. Lin, H. Zheng, Z. Zhu, H. David, and Z. Zhang. Thermal modeling and management
of dram memory systems. In Proceedings of the 34th annual international symposium
on Computer Architecture (ISCA'07), pages 312-322, 2007.
[10] X. Zhou, J. Yang, Y. Zhang, and J. Zhao. Thermal-aware task scheduling for 3d mul-
ticore processors. In IEEE Transactions on Parallel and Distributed Systems, pages
60-71, 2009.
[11] S. Liu, B. Leung, A. Neckar, S. O. Memik, G. Memik, and N. Hardavellas. Hardware/-
software techniques for dram thermal management. In 17th International Conference
on High-Performance Computer Architecture (HPCA-17), pages 515-525, 2011.
[12] C.-H. Lin, C.-L. Yang, and K.-J. King. Ppt: Joint performance/power/thermal man-
agement of dram memory for multi-core systems. In Proceedings of the 34th annaual
International Symposium on Computer Architecture, pages 93-98, 2009.
[13] Q. Deng, D. Meisner, and A. Bhattacharjee. Mutiscale: Memory system dvfs with
multiple memory controllers. In Proceedings of the 2012 ACM/IEEE International
Symposium on Low power electronics and design (ISLPED'12), pages 297-302, 2012.
[14] Shu-Yen Lin and Jin-Yi Lin. Thermal-aware architecture and mapping for multi-channel
three-dimensional dram systems. In IEEE 3rd Global Conference on Consumer Elec-
tronics, pages 713-714, 2014.
[15] E. ALPAYDIN. Introduction to machine learning, 2nd ed. mit press.
[16] P. Magnusson et al. Simics: A full system simulation platform. 2002.
[17] M. M. K. Martin et al. Multifacets general execution-driven multiprocessor simulator
(gems).
[18] B. Jacob E. Cooper-Balis, P. Rosenfeld. Buer-on-board memory systems. In ISCA'12,
pages 392-403, 2012.
[19] R. J. Rib M. R. Stan K. Skadron W. Huang, K. Sankaranarayanan. An improved block-
based thermal model in hotspot 4.0 with granularity considerations. In Proceedings of
the Workshop on Duplicating, Deconstructing, and Debunking, 2007.
[1] O. Mutlu M. Kandemir Thomas Moscibroda S. P. Muralidhara, L. Subramanian. Re-
ducing memory interference in multicore systems via application-aware memory channel
partitioning. In MICRO'11, pages 374{385, 2011.
[2] Wm. A. Wulf and Sally A. McKee. Hitting the memory wall: Implications of the
obvious. In ACM SIGARCH Computer Architecture News, pages 20{24, 1995.
[3] J. Jeddeloh and B. Keeth. Hybrid memory cube new dram architecture increases density
and performance. In VLSI Technology (VLSIT), 2012 Symposium, pages 87{88, 2012.
[4] B. Black, D. W. Nelson, C. Webb, and N. Samra. 3d processing technology and its
impact on ia32 microprocessors. In Proceedings of ICCD, pages 316{318, 2004.
[5] K. Banerjee, A. Mehrotra, A. Sangiovanni-Vincentelli, and Hu Chenming. Thermal
eects in deep submicron vlsi interconnects. In Design Automation Conference (DAC),
pages 885{891, 1999.
[6] S. Zhang and Z. Zhu. Access-aware memory thermal management. In IEEE Inter-
national Conference on Networking, Architecture and Storage (NAS), pages 268{274,
2014.
[7] M. J. Khurshid and M. Lipasti. Data compression for thermal mitigation in the hybrid
memory cube. In ICCD'13, pages 185{192, 2013.
28
[8] A.-C. Hsieh and T.-T. Hwang. Thermal-aware memory mapping in 3d designs. In
DATE'09, pages 1361{1366, 2009.
[9] J. Lin, H. Zheng, Z. Zhu, H. David, and Z. Zhang. Thermal modeling and management
of dram memory systems. In Proceedings of the 34th annual international symposium
on Computer Architecture (ISCA'07), pages 312{322, 2007.
[10] X. Zhou, J. Yang, Y. Zhang, and J. Zhao. Thermal-aware task scheduling for 3d mul-
ticore processors. In IEEE Transactions on Parallel and Distributed Systems, pages
60{71, 2009.
[11] S. Liu, B. Leung, A. Neckar, S. O. Memik, G. Memik, and N. Hardavellas. Hardware/-
software techniques for dram thermal management. In 17th International Conference
on High-Performance Computer Architecture (HPCA-17), pages 515{525, 2011.
[12] C.-H. Lin, C.-L. Yang, and K.-J. King. Ppt: Joint performance/power/thermal man-
agement of dram memory for multi-core systems. In Proceedings of the 34th annaual
International Symposium on Computer Architecture, pages 93{98, 2009.
[13] Q. Deng, D. Meisner, and A. Bhattacharjee. Mutiscale: Memory system dvfs with
multiple memory controllers. In Proceedings of the 2012 ACM/IEEE International
Symposium on Low power electronics and design (ISLPED'12), pages 297{302, 2012.
[14] Shu-Yen Lin and Jin-Yi Lin. Thermal-aware architecture and mapping for multi-channel
three-dimensional dram systems. In IEEE 3rd Global Conference on Consumer Elec-
tronics, pages 713{714, 2014.
[15] E. ALPAYDIN. Introduction to machine learning, 2nd ed. mit press.
[16] P. Magnusson et al. Simics: A full system simulation platform. 2002.
[17] M. M. K. Martin et al. Multifacets general execution-driven multiprocessor simulator
(gems).
29
[18] B. Jacob E. Cooper-Balis, P. Rosenfeld. Buer-on-board memory systems. In ISCA'12,
pages 392{403, 2012.
[19] R. J. Rib M. R. Stan K. Skadron W. Huang, K. Sankaranarayanan. An improved block-
based thermal model in hotspot 4.0 with granularity considerations. In Proceedings of
the Workshop on Duplicating, Deconstructing, and Debunking, 2007.
[20] D. Rossell J. Meng and A. K. Coskun. Exploring performance, power, and temperature
characteristics of 3d systems with on-chip dram. In IGCC'11, pages 1-6, 2011.