快速測試整合：建構於IEEE 1500標準測試封套介面之SOC內嵌式多重時脈之隨差即用延遲錯誤測試系統

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研究生：	陳柏霖 Chen, Po-Lin
論文名稱：	快速測試整合：建構於IEEE 1500標準測試封套介面之SOC內嵌式多重時脈之隨差即用延遲錯誤測試系統 Fast Test Integration: Toward Plug-and-Play Embedded At-speed Test Framework for Multiple Clock Domains in System-On-Chips Based on IEEE Standard 1500
指導教授：	張慶元 Chang, Tsin-Yuan
口試委員:	張慶元張彌彰劉靖家陳竹一李進福鄭經華
學位類別：	博士 Doctor
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2011
畢業學年度：	99
語文別：	英文
論文頁數：	93
中文關鍵詞：	at-speed testing 、delay testing 、SoC testing 、IEEE 1500 、multiple clock domain
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Rapid advances in semi-conductor technology have made timing-related defects increasingly crucial in core-based system-on-chip designs. Currently, modular test strategies based on IEEE std.1500 are applied to test the functionality of each embedded core in SOC designs but fail to verify the corresponding timing specifications. To achieve high quality of delay tests, hardware implementation of an embedded at-speed (delay) test framework including the modified test wrappers and the Embedded At-speed (delay) test Mechanism is presented to build an entirely embedded at-speed (delay) test environment where at-speed clock is applied inside the chip to increase test accuracy. The proposed at-speed (delay) test framework is also capable of supporting all current solutions of core-based delay test. The experimental results successfully demonstrate the delay testing application for single clock domain using the proposed framework to a Crypto Processor with satisfying test quality and effectiveness.
However, current design strategies which integrated blocks operating different clock frequencies still may exposes designs even with aforementioned at-speed (delay) test framework to severe reliability loss due to incomplete at-speed testing which is induced by ignorance of timing-related defects between clock domains. Further, the reduced testability caused by core-based design strategy also aggravates the difficulty in applying on-chip at-speed testing. Although previous works were able to successfully increase the quality of the at-speed testing for single clock, defects between clock domains still remain undiscovered and the diversity of on-chip clock control schemes from different components may complicate the test integration, increasing the test costs. Therefore, to accelerate the time-to-market and the time-to-volume, the development of a Plug-and-Play at-speed testing based on a well-defined test interface has become increasingly urgent. In this dissertation, a fast test integration approach for multi-clock-domain at-speed testing based on IEEE Standard 1500 is proposed. The proposed framework has been successfully integrated into an IEEE 1500-wrapped ultra-wide-band design and a simple SOC design. Experiment results also confirm the feasibility of the proposed approach. And to achieve “Fast-Test-Integration”, an automation tool has also been established.

隨著製程技術的不斷提升，晶片速度持續攀高，與時序(timing)相關的延遲缺陷(delay defects)，例如電阻短路、電阻斷路或者是訊號完整性問題，也逐漸了主宰晶片測試的品質(test quality)。然而，以傳統偵測定值錯誤(Stuck-at fault)為主流的測試方法並無法有效的檢測出時序相關的延遲缺陷，因此無法驗證晶片是否能夠操作在設計規格(design specifications)所規範的功能時脈速度(functional clock speed) 。單單依靠傳統定值錯誤測試不僅僅降低測試效率也額外增加測試負擔與成本(test cost)。因此，為解決時序相關的延遲缺陷所導致的後段測試的困難，半導體業界發展出相對應單一時脈域(single clock domain)延遲錯誤測試(delay fault test)或者稱全速測試(at-speed test)來針對單一頻率待測電路的延遲錯誤測試。然而，製程技術的快速發展也促使系統晶片(System-on-Chip)的設計策略得以整合多顆具有高效能、多重時脈(multiple clock domain)的設計於其中。跨頻域CDC (Clock Domain Crossing)的資料傳輸模式也促使延遲錯誤測試必須從原本單一時脈域的延遲測試延伸至多重時脈域且跨時脈域的延遲錯誤測試，以確保整體延遲錯誤測試的品質。
然而，針對高速且多重時脈域的系統晶片的延遲錯誤測試已非傳統低階自動測試機台(Automatic Test Equipment)所能支援，因此，內嵌式可支援延遲錯誤測試的可測性設計(Design-for-Testability)變得相當重要與熱門，尤其在SOC設計模式的考量下，所有的邏輯電路皆內嵌在其中，無法由chip level的I/Os所控制與觀察，如何在chip內部執行多重時脈域的延遲錯誤測試，變得困難重重。雖然由美國電子電機工程師學會(Institute of Electrical and Electronic Engineers, IEEE)所提出模組化的系統晶片測試標準(IEEE Standard 1500)來對SOC中內嵌的邏輯電路(embedded cores)作有效的測試，但是並無提供任延遲測試相關之解決方案。因此，如何針對現有IEEE 1500所規範的測試標準之下，提出具有低面積開銷(low area overhead)、強健性(robustness)、且具有支援多重時脈域延遲錯誤測試的內嵌可測性設計來提升整體延遲錯誤測試的測試品質及可靠度並且降低測試成本為現階段提升系統晶片測試品質非常重要的部份。

Acknowledgement (in Chinese)…………………………………………………… ..I
Abstract (in Chinese)………………….…………………………………………….II
Abstract (in English)………………………………………………………………..IV
List of Contents……………………………………………………………………..VI
List of Figures……………………………………………………………………….IX
List of Tables……………………………………………………………………….XII


1  Introduction                                                      1
1.1  At-Speed Testability Enhancement for Core-Based SoCs Based on IEEE std.1500……………………………………………………………………...1
1.2  Further Enhancement of IEEE Std. 1500 by Considering Multiple Clock Domain Issue………………………………………………………………..4
1.3  Organization of the Dissertation……………………………………………. 6
2  Preliminaries:
At-speed (delay) test FRAMEWORK Based on IEEE 1500 Standard       7
2.1  Introduction of IEEE 1500…………………………………………………. 7
2.1.1  Core Test Language (CTL)………………………………………... 8
2.1.2  Overview of IEEE Std. 1500………………………………………. 8
2.2  Necessity of Adopting Pattern-Pair Test Patterns for Higher Delay Fault Coverage………………………………………………………………...... 10
2.2.1  Two-Pattern Test of Core-based SoC designs Based On Parallel-Controlled Primary Inputs………………………………. 12
2.2.2  STEAC: A Platform for Automatic SOC Test Integration………. 15
2.2.3  Summary…………………………………………………………. 16

2.3  Multiple Clock Domain At-Speed Testing in Core-based SOC Designs… 17
2.3.1  A Novel and Practical Control Scheme for Inter-Clock At-Speed Testing……………………………………………………………. 20
2.3.2  An On-Chip Test Clock Control Scheme for Multi-clock At-Speed Testing……………………………………………………………. 23
      2.3.3  Summary…………………………………………………………. 27
3  At-Speed Testing Concerns and Modification of the IEEE Std 1500 Test Wrapper                                                        28
3.1  At-Speed Testing Issues in Test Wrapper Cells…………………………... 28
3.2  Clock Distribution of Proposed Test Wrapper……………………………. 30
3.3  Control Circuitry Modification and Delay Testing Sequences…………… 32

4  Proposed Embedded At-Speed (Delay) Test Mechanism for Single Clock Domain At- Speed Testing                                         35
4.1  Tap-like Controller………………………………………………………... 35
4.2  Delay-test-aware Clock Controller………………………………………... 39
5  The Embedded At-Speed (Delay) Test Framework for Multiple Clock
Domains At-Speed Testing                                         43
5.1  Clock Control Scheme of the Wrapper Boundary Registers and Enhancement of Wrapper Instruction Registers………………………….. 46
5.2  Clock Signal Controller…………………………………………………… 47
5.3  Delay-Test-Aware Clock Controller With Support for Multi
-Clock-Domains………………………………………………………….. 50
6  At-speed (delay) test Scheduling and Wrapper Scan Chain Design        59
6.1  Wrapper Scan Design for Delay Testing………………………………….. 59
6.2  Test Application Time Estimation………………………………………... 62
6.3  At-speed (delay) test Schedule and Test Application Time………………. 66




7  Case Study                                                      69
7.1  Application of At-Speed Testing to Embedded Cores with Single Clock Domain…………………………………………………………………… 69
7.2  Application of At-Speed Testing to Embedded Cores with Multiple Clock
Domains………………………………………………………………………….. 76
8  Conclusion                                                      83
Bibliography                                                       85
















List of Figures

Fig. 2.1   Core test wrapper interface [37]………………………………………….. 9
Fig. 2.2   Standard IEEE wrapper components [5]…………………………………10
Fig. 2.3   (a) Currently-Used Wrapper Cells: Regular wrapper input cell (WIC) (b) Enhanced wrapper boundary register (c) Modified wrapper cell [16]….. 13
Fig. 2.4   Two-pattern test of core-based SoCs (a) Session 1: core 1 and core 2 as producers (b) Session 2: core 3 as producer [18]……………………….. 14
Fig. 2.5   At-speed testing issues of Multiple clock domain……………………… 19
Fig. 2.6   Test architecture of inter-clock test control scheme……………………. 22
Fig. 2.7   Schematic of inter-clock enable generator……………………………… 22
Fig. 2.8   General architecture of the proposed on-chip clock control scheme…… 24
Fig. 2.9   Detailed structure of proposed clock generator………………………… 25
Fig. 2.10  Theoretical analysis on the number of flip-flops required in the proposed method with the increase in the number of clock domains………………26
Fig. 2.11  The area overhead for three different benchmark circuits……………… 26
Fig. 3.1   Timing Precision of Clock Alignment between HCLK and WRCK…… 29
Fig. 3.2   Proposed At-speed (delay) test Wrapper and Clock Inversion Mechanism ………………………………………………………………31
Fig. 3.3   Control System Modification of WIR……………………………………33
Fig. 3.4   Delay fault testing Sequences for Modified Test Wrapper……………... 34
Fig. 4.1   State Diagram of Proposed TAP-like Controller……………………….. 36
Fig. 4.2   Corresponding At-speed (delay) test Operation According to the State of EDTM…………………………………………………………………… 38
Fig. 4.3   Delay-test-aware Clock Controller……………………………………... 40
Fig. 4.4   At-speed (delay) test Waveform………………………………………... 42
Fig. 5.1   The Embedded at-speed clock control mechanism for at-speed testing of multiple clock domains…………………………………………………. 43
Fig. 5.2   Multi-clock at-speed testing issues……………………………………... 45
Fig. 5.3   Associated test waveforms of test wrappers and internal scan chains for corresponding domain-under-test………………………………………. 49
Fig. 5.4   Delay-test-aware clock controller for at-speed testing of multiple clock domains…………………………………………………………………. 50
Fig. 5.5   Delay-test-aware clock controller for at-speed testing of multiple clock domains…………………………………………………………………. 52
Fig. 5.6   State diagrams of FSM_N1 and FSM_N2……………………………… 55
Fig. 5.7   Timing adjustor and the correspond timing interval between launch and capture…………………………………………………………………... 56
Fig. 5.8   Waveforms of Generation of Two Normal Clock Pulses [62]…………. 57
Fig. 5.9   Test waveform of at-speed testing of inter-clock domains…………….. 58
Fig. 6.1   Design Strategies of Wrapper Scan Chain……………………………… 61
Fig. 7.1   Chip level View of the Benchmark SOC……………………………….. 74
Fig. 7.2   Core level View of the CUT……………………………………………. 75
Fig. 7.3   Test Chip of the RNG…………………………………………………... 75
Fig. 7.4   A simple IEEE 1500-wrapped SoC design equipped with proposed at-speed (delay) test framework………………………………………… 77
Fig. 7.5   Core-level view of the CUT……………………………………………. 80
Fig. 7.6   Experiment results measured by Logic Analyzer (LA2164P-2M) compared with simulation results obtained by Nanosim for the nineteenth test pattern of RNG1……………………………………………………. 80
Fig. 7.7   Experiment results measured by Logic Analyzer (LA2164P-2M) compared with simulation results obtained by Nanosim for the twentieth test pattern of RNG1……………………………………………………. 81
Fig. 7.8   Experiment results measured by Agilent 93000 provided by CIC……... 81
Fig. 7.9   Shmoo plot measured by Agilent 93000 provided by CIC…………….. 82
























List of Tables

Table 2.1  Delay fault coverage comparison: Single patter test vs. Pattern-Pair test pattern………………………………………………………………….. 11
Table 2.2  Test results of at-speed testing for inter-clock domain logics………….. 23
Table 6.1  Test Application Time of Proposed At-speed (delay) test Framework for g1023…………………………………………………………………... 64
Table 6.2  Test Application Time of Proposed At-speed (delay) test Framework for p22810…………………………………………………………………. 64
Table 6.3  Test Application Time of Proposed At-speed (delay) test Framework for p93791…………………………………………………………………. 65
Table 6.4  Test Application Time of Proposed At-speed (delay) test Framework for p34392…………………………………………………………………. 65
Table 7.1  Summary of Cores Area in CP (um2)…………………………………… 70
Table 7.2  Test Information of Core-Under-Test………………………………….. 71
Table 7.3  Test Scheduling Results for Crypto Processor…………………………. 71
Table 7.4  Comparison of the At-speed (delay) test Framework………………….. 73
Table 7.5  Comparison of Area Overhead of At-Speed Test Frameworks………… 78

                                

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