著近年來多核心架構逐漸成為嵌入式系統之主要硬體架構，其不斷增長的
平行硬體設計，使得系統軟體之效能成為開發嵌入式多核心應用軟體之一關
鍵議題。在設計與實作嵌入式多核心系統軟體上，有以下幾方面之挑戰：有
效之程式設計模型、高效能之執行期系統、以及平行軟體之測試及驗證。

本論文解決在設計及實作高效能多核心系統軟體之挑戰。首先，討論在平行
化應用軟體時所會遭遇到之問題，並提出一有效之程式設計模型來展現應用
軟體中之平行度。此程式設計環境不只考慮在撰寫上之簡易性，同時亦考量
其效能及日後維護上之相關問題。此程式設計模型包含一資料串流技巧，此
技巧透過資料串流之技術提供多媒體應用軟體之最佳化。同時此程式設計
模型也提供程式設計樣板以展現此程式設計模型之使用方法。

第二，本論文提出一多核心系統上之作業系統及溝通函式庫之設計與實作。
此作業系統透過降低文本交換之技術以提高其在執行期之效能。最後本論
文介紹一自動之測試及驗證系統。此驗證系統透過一正規表示法之描述檔描
述系統之執行期運作狀況來自動產生測試檔案來模擬執行期之系統執行狀態
。本論文亦展示其測試流程。

系統軟體對於嵌入式多核心應用軟體之開發是一關鍵技術。本論文所探討之
技術著重於以下幾點議題：如何設計程式開發環境、最佳化執行期系統之效
能、以及軟體之測試及驗證。本論文提出一多核心系統上之系統軟體架構，
包含其設計及實作上之相關議題，同時並討論了如何架構一高效能之嵌入式
多核心系統軟體。

Trends of embedded system development
recently point toward multicore architecture
with increasingly parallel hardwares.
Efficient system software is
becoming a critical aspect of
developing multicore applications for embedded systems.
There are challenges associates to the system software design and implementation
for embedded multicore processors,
effective programming model,
efficient runtime system,
and testing of concurrent softwares.

This dissertation tackles the challenges of designing
and implementing high performance system software for
multicore processors.
First,
it
examines the issues of parallelizing application
on multicore processors
and then
presents
an effective programming model
to extract the parallelism in the applications.
The programming environment
considers not
only the programmability
but also the performance and maintenance of
the applications.
The programming model
contains
a data streaming technique
for optimizing multimedia applications
to reduce the communication overhead.
The programming environment
also contains
design patterns
that demonstrates
the usage of the programing model.

Second,
this dissertation
illustrates the design and implementation
of the operating system and communication library.
The operating system adapts a technique of reducing the
context switch overhead during task switching
for optimizing the performance of operating system.
Finally, this dissertation introduce
an automatic testing and verification tool, pTest,
for testing the concurrent multicore softwares.
pTest contains a formal representation to generate
testing patterns for
testing the runtime execution behavior.
The experiments demonstrate the testing tool
by evaluating the development flow
of the programing environment.

System software
is a key factor to the efficiency of embedded multicore
applications.
The technique presented in this article address
the issues of designing the programming environment,
optimizing the overhead of runtime system,
and verifying the current applications.
This dissertation presents
the design and implementation
of efficient system software for multicore processors
and discusses
issues and solution of
building efficient system software for multicore processors.

[1] ITRS. International technology roadmap for semiconductors exectutive summary,
2008.
[2] Wayne Wolf. The future of multiprocessor systems-on-chips. In Proceedings of
the 41st annual conference on Design automation, pages 681–685, 2004.
[3] Grant Martin. Overview of the MPSoC design challenge. In Proceedings of
Design Automation Conference, pages 274–279, 2006.
[4] L. Dagum and R. Menon. Openmp: an industry standard api for shared-memory
programming. Computational Science I& Engineering, IEEE, 5(1):46–55, Jan-
Mar 1998.
[5] William Gropp and Ewing L. Lusk. A high-performance mpi implementation on
a shared-memory vector supercomputer. Paral lel Computing, 22(11):1513–1526,
1997.
[6] Tom R. Halfhill. Parallel processing with cuda. MICROPROCESSOR, 2008.
[7] Ana Lucia Varbanescu, Maik Nijhuis, Arturo Gonzalez-Escribano, Henk J. Sips,
Herbert Bos, and Henri E. Bal. Sp@ce - an sp-based programming model for
consumer electronics streaming applications. In LCPC, pages 33–48, 2006.
[8] William Thies, Michal Karczmarek, and Saman Amarasinghe. Streamit: A lan-
guage for streaming applications. In Proceedings of Computational Complexity,
pages 179–196, 2002.
[9] David Chih-Wei Chang, I-Tao Liao, Jenq-Kuen Lee, Wen-Feng Chen, Shau-
Yin Tseng, and Chein-Wei Jen. PAC DSP core and application processors. In
Proceedings of IEEE International Conference on Multimedia and Expo, pages
289–292, 2006.
[10] Texas Instruments Inc. TMS320 DSP/BIOS User’s Guide, NOV 2001.
111
BIBLIOGRAPHY 112
[11] Tay-Jyi Lin, Chen-Chia Lee, Chih-Wei Liu, and Chein-Wei Jen. A novel reg-
ister organization for vliw digital signal processors. In 2005 IEEE VLSI-TSA
International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-
TSA-DAT), pages 337–340, 2005.
[12] Scott Rixner, William J. Dally, Brucek Khailany, Peter Mattson, Ujval J. Kapasi,
and John D. Owens. Register organization for media processing. In Proceedings of
International Symposium on High Performance Computer Architecture (HPCA),
pages 375–386, 2000.
[13] Seng Lin Shee, Andrea Erdos, and Sri Parameswara. Heterogeneous multiproces-
sor implementations for jpeg: a case study. In Proceedings of the 4th international
conference on Hardware/software codesign and system synthesis, pages 217–222,
2006.
[14] Orit Edelstein, Eitan Farchi, Evgeny Goldin, Yarden Nir, Gil Ratsaby, and
Shmuel Ur. Framework for testing multi-threaded java programs. Concurrency
and Computation: Practice and Experience, 15(3-5):485–499, February 2003.
[15] Madanlal Musuvathi and Shaz Qadeer. Fair stateless model checking. In Proceed-
ings of the 2008 ACM SIGPLAN conference on Programming language design
and implementation, pages 362–371, 2008.
[16] Edmund M. Clarke, Orna Grumberg, and Doron A. Peled. Model Checking. MIT
Press, 2000.
[17] Alex Groce and Ra jeev Joshi. Random testing and model checking: building a
common framework for nondeterministic exploration. In Proceedings of the 2008
international workshop on dynamic analysis: held in conjunction with the ACM
SIGSOFT International Symposium on Software Testing and Analysis (ISSTA
2008), pages 22–28, 2008.
[18] Enrique Vidal, Frank Thollard, Colin de la Higuera, Francisco Casacuberta, and
Rafael C. Carrasco. Probabilistic finite-state machines-part i. IEEE Transactions
on Pattern Analysis and Machine Intel ligence, 27(7):1013–1025, July 2005.
[19] Enrique Vidal, Frank Thollard, Colin de la Higuera, Francisco Casacuberta, and
Rafael C. Carrasco. Probabilistic finite-state machines-part ii. IEEE Transac-
tions on Pattern Analysis and Machine Intel ligence, 27(7):1026–1039, July 2005.
[20] Kun-Yuan Hsieh, Yung-Chia Lin, and Jenq Kuen Lee. Enhancing microkernel
performance on VLIW DSP processors via multiset context switch. Journal of
Signal Processing Systems, 51(3):257–268, June 2008.
BIBLIOGRAPHY 113
[21] Kun-Yuan Hsieh, Yen-Chih Liu, Po-Wen Wu, Shou-Wei Chang, and Jenq Kuen
Lee. Enabling streaming remoting on embedded dual-core processors. In Pro-
ceedings of the 37th International Conference on Paral lel Processing (ICPP’08),
2008.
[22] Kun-Yuan Hsieh, Yen-Chih Liu, Chi-Hua Lai, and Jenq Kuen Lee. The support
of software design patterns for streaming rpc on embedded multicore processors.
In SiPS, pages 263–268. IEEE, 2008.
[23] Kun-Yuan Hsieh, Chi-Hua Lai, Shang-Hon Lai, and Jenq Kuen Lee;. Paralleliza-
tion of belief propagation method on embedded multicore processors for stereo
vision. In ACM Transaction on Embedded Systems, pages 39–44, 2008.
[24] Chi Wu, Kun-Yuan Hsieh, Yung-Chia Lin, Chung-Ju Wu, Wen-Li Shih, S. C.
Chen, Chung-Kai Chen, Chien-Ching Huang, Yi-Ping You, and Jenq Kuen Lee.
Integrating compiler and system toolkit flow for embedded VLIW DSP proces-
sors. In Proceedings of IEEE International Conference on Embedded and Real-
Time Computing Systems and Applications, pages 215–222, 2006.
[25] Shou-Wei Chang, Kun-Yuan Hsieh, and Jenq Kuen Lee. ptest: An adaptive
testing tool for concurrent software on embedded multicore processors. In DATE,
pages 1012–1017. IEEE, 2009.
[26] Chung-Wen Huang, Kun-Yuan Hsieh, Jia-Jhe Li, and Jenq Kuen Lee. Support
of paged register files for improving context switching on embedded processors.
In Proceedings of the 7th IEEE/IFIP International Conference on Embedded and
Ubiquitous Computing, 2009.
[27] Cheng-Yen Lin, Shao-Chung Wang, Ming-Yu Hung, Kun-Yuan Hsieh, and
Jenq Kuen Lee. Software cache support and api design for embedded dsp pro-
cessors. In Proceedings of International SoC Design Conference 2009, 2009.
[28] Don Murray and James J. Little. Using real-time stereo vision for mobile robot
navigation. Autonomous Robots, 8(2):161–171, 2000.
[29] Jun Miura, Yoshiro Negishi, and Yoshiaki Shirai. Mobile robot map generation by
integrating omnidirectional stereo and laser range finder. Intel ligent Robots and
System, 2002. IEEE/RSJ International Conference on, 1:250–255 vol.1, 2002.
[30] J.M. Porta, J.J. Verbeek, and B.J.A. Krose. Active appearance-based robot
localization using stereo vision. Autonomous Robots, 18(1):59–80, 2004.
BIBLIOGRAPHY 114
[31] YoungSu Kim, SungChan Park, Chao Chen, and Hong Jeong. Real-time ar-
chitecture of stereo vision for robot eye. In Proceedings of 8th International
Conference on Signal Processing, volume 1, 2006.
[32] Jain Sun, Nan-Ning Zheng, and Heung-Ywung Shum. Stereo matching using
belief propagation. IEEE Tansaction on Pattern Analysis and Machine Intel li-
gence, 25(7):787–800, 2003.
[33] Jonathan S. Yedidia, William T. Freeman, and Yair Wiess. Constructing free-
energy approximations and generalized belief propagation algorithms. IEEE
Transaction on Information Theory, 51(7):2282–2312, 2005.
[34] Pedro F. Felzenszwalb and Daniel P. Huttenlocher. Efficient belief propagation
for early vision. International Journal of Computer Vision, 70(1):41–54, 2006.
[35] Alan Brunton, Chang Shu, and Gerhard Roth. Belief propagation on the GPU
for stereo vision. In Proceedings of the 3rd Canadian Conference on Computer
and Robot Vision, pages 76–81, June 2006.
[36] A. Mendiburu, R. Santana, J. A. Lozano, and E. Bengoetxea. A parallel frame-
work for loopy belief propagation. In Proceedings of the 2007 GECCO Conference
Companion on Genetic and Evolutionary Computation, pages 2843–2850, July
2007.
[37] Michael Gschwind. The Cell broadband engine: Exploiting multiple levels of
parallelism in a chip multiprocessor. International Journal of Paral lel Processing,
35(3):233–262, 2007.
[38] Richard I. Hartley. Theory and practice of pro jective rectification. International
Journal of Computer Vision, 35(2):115–127, 1999.
[39] IBM. Cel l Broadband Engine Programming Handbook version 1.1, 2007.
[40] K. Mani Chandy and Jayadev Misra. Paral lel Program Design: A Foundation.
Addison Wesley Publishing Company, Inc., Reading, Massachusetts, 1988.
[41] A. K. Singh. Parallel programming: Achieving portability through abstraction.
In 11th International Conference on Distributed Computing Systems, May 1991.
[42] Michael D. McCool. Data-parallel programming on the Cell BE and the GPU us-
ing the rapidmind development platform. In Proceedings of 2006 GSPx Multicore
Applications Conference, 2006.
BIBLIOGRAPHY 115
[43] Michael D. Linderman, Jamison D. Collins, Hong Wang, and Teresa H. Meng.
Merge: a programming model for heterogeneous multi-core systems. In ASPLOS
XIII: Proceedings of the 13th international conference on Architectural support
for programming languages and operating systems, pages 287–296, New York,
NY, USA, 2008. ACM.
[44] Yen-Kuang Chen, Wenlong Li, and Xiaofeng Tong. Parallelization of AdaBoost
algorithm on multi-core processors. In Proceedings of 2008 IEEE Workshop on
Signal Processing Systems, pages 275–280, 2008.
[45] Mahsan Rofouei, Maryam Moazeni, and Ma jid Sarrafzadeh. Fast GPU-based
space-time correlation for activity recognition in video sequences. In Proceedings
of the 2008 IEEE Workshop on Embedded Systmes for Real-time Multimedia,
pages 33–38, 2008.
[46] Seunghwa Kang and David A. Bader. Optimizing JPEG2000 still image encoding
on the cell broadband engine. In Proceedings of the 37th International Conference
on Paral lel Processing, pages 83–90, 2008.
[47] F. Petrini, G. Fossum, J. Fernandez, A.L. Varbanescu, M. Kistler, and M. Per-
rone. Multicore surprises: Lessons learned from optimizing sweep3d on the cell
broadband engine. In IPDPS2007, volume CDROM, pages 1–10. IEEE Society,
March 2007.
[48] Ross Kindermann and J. Laurie Snell. Markov random fields and their applica-
tions. AMS, 1980.
[49] Yair Wiess and William T. Freeman. On the optimality of solutions of the max-
product belief-propagation algorithm in arbitrary graphs. IEEE Transactions on
Information Theory, 47(2):723–735, 2001.
[50] Qingxiong Yang, Liang Wan, Ruigang Yang, Shengnan Wang, Miao Liao, and
David Nister. Real-time global stereo matching using hierarchical belief propa-
gation. In Proceedings of the British Maching Vision Conference, 2006.
[51] Dana S. Henry. Hardware mechanisms for efficient interprocessor communica-
tion. PhD thesis, Massachusetts Institute of Technology. Dept. of Electrical
Engineering and Computer Science, 1996.
[52] Brian N. Bershad, Thomas E. Anderson, Edward D. Lazowska, and Henry M.
Levy. User-level interprocess communication for shared memory multiprocessors.
ACM Transactions on Computer Systems, 9(2):175–198, 1991.
BIBLIOGRAPHY 116
[53] Steve Preissig. Programming details of codec enging for DaVinci Techonology
whitepaper. Texas Instuments.
[54] Erich Gamma, Richard Helm, Ralph Johnson, and John Vlissides. Deisng Pat-
terns: Elements of Reusable Object-Oriented Software. Addison-Wesley, 1995.
[55] Michael R. Garey and David S. Johnson. Computers and Intractability: A Guide
to the Theory of NP-Completen. W. H. Freeman & Co., 1990.
[56] Silvano Martello and Paolo Toth. Knapsack Problems: Algorithms and Computer
Implementations. John Wiley & Sons, 1990.
[57] M. D. Bachurina, S. V. Beletskii, and V. Ts. Levental. Pseudopolynomial algo-
rithms for the solution of backpack problems. Journal of Mathematical Sciences,
65(1):1464–1468, 1993.
[58] Ian Buck, Tim Foley, Daniel Horn, Jeremy Sugerman, Kayvon Fatahalian, Mike
Houston, and Pat Hanrahan. Brook for gpus: Stream computing on graphics
hardware. ACM Transactions on Graphics, 23(3):777–786, 2004.
[59] William R. Mark, R. Steven Glanville, Kurt Akeley, and Mark J. Kilgard. Cg:
A system for programming graphics hardware in a C-like language. In Proceed-
ings of the 30th International Confernce on Computer Graphics and Interactive
Techniques, pages 896–907, 2003.
[60] Scott Rixner, William J. Dally, Ujval J. Kapasi, Brucek Khailany, Abelardo
Lopez-Lagunas, Peter R. Mattson, and John D. Owens. A bandwidth-efficient
architecture for media processing. In Proceedins of 31th International Symposium
on Microarchitecture, pages 3–13, Mar 1998.
[61] Ujval J. Kapasi, Scott Rixner, William J. Dally, Brucek Khailany, Jung Ho Ahna
dnd Peter Mattson, and John D. Owens. Programmable stream processors.
Computer, 36(8):54–62, 2003.
[62] Sankalita Saha, Jason, Schlessman, Sebastian Puthenpurayil, Shuvra S. Bhat-
tacharyya, and Wayne Wolf. An optimized message passing framework for par-
allel implementation of signal processing applications. Design, Automation and
Test in Europe, 2008. DATE ’08, pages 1220–1225, March 2008.
[63] Pieter Bellens, Josep M. Perez, Rosa M. Badia, and Jesus Labarta. Cellss: a
programming model for the cell be architecture. Supercomputing, 2006. SC ’06.
Proceedings of the ACM/IEEE SC 2006 Conference, pages 5–5, 2006.
BIBLIOGRAPHY 117
[64] A. E. Eichenberger, J. K. O’Brien, K. M. O’Brien, P. Wu, T. Chen, P. H. Oden,
D. A. Prener, J. C. Shepherd, B. So, Z. Sura, A. Wang, T. Zhang, P. Zhao, M. K.
Gschwind, R. Archambault, Y. Gao, and R. Koo. Using advanced compiler tech-
nology to exploit the performance of the cell broadband enginetm architecture.
IBM Syst. J., 45(1):59–84, 2006.
[65] Kayvon Fatahalian, Timothy J. Knight, Mike Houston, Mattan Erez, Daniel Re-
iter Horn, Larkhoon Leem, Ji Young Park, Manman Ren, Alex Aiken, William J.
Dally, and Pat Hanrahan. Sequoia: Programming the memory hierarchy. sc, 0:4,
2006.
[66] Michael D. McCool. Data-parallel programming on the cell be and the gpu
using the rapidmind development platform. In Proceedings of GSPx Multi-core
Applicaion Conference, 2006.
[67] D. Zhang, Q. Li, R. Rabbah, and S. Amarasinghe. A lightweight streaming layer
for multicore execution. In Workshop on Design, Architecture, and Simulation
of Chip Multiprocessors, 2007.
[68] Jayanth Gummara ju, Joel Coburn, Yoshio Turner, and Mendel Rosenblum.
Streamware: Programming gerneral-purpose multicore processor using streams.
ACM SIGOPS Operating System Review, 42(2):297–307, Mar 2008.
[69] Chih-Chieh Yang, Chung-Kai Chen, Yu-Hao Chang, Kai-Hsin Chung, and Jenq-
Kuen Lee. Streaming support for Java RMI in distributed environment. In
Proceedings of ACM International Conference on Principles and Practices of
Programming In Java, pages 53–61, 2006.
[70] DSPLinux Board Support Package.
[71] Texas Instruments Inc. DSP/BIOS Real-Time Kernel and DSP/BIOS Link Tech-
nology, NOV 2001.
[72] T.I. OMAP5912 Application Processor. Texas Instuments, 12 2005.
[73] Steve Muir and Jonathan Smith. Asymos - an asymmetric multiprocessor oper-
ating system. In In IEEE Conf on Open Architectures and Network Programming
(OPENARCH, pages 25–34, 1998.
[74] Jeffrey S. Chase, Henry M. Lery, Michael J. Feeley, and Edward D. Lazowska.
Sharing and protection in a single-address-space operating system. CM Trans-
actions on Computer Systems, 12(4):271–307, 1994.
BIBLIOGRAPHY 118
[75] Lui Sha, Ragunathan Ra jkumar, and John P. Lehoczky. Priority inheritance
protocols: An approach to real-time synchronization. Transaction on Computers,
39(9):1175–1185, 1990.
[76] Texas Instruments. DSP/BIOS Timing Benchmarks for Code Composer Studio
v2.2 Application Report SPRA900B, April 2004.
[77] Jamil Chaoui. OmapTM: Enabling multimedia applications in third generation
(3g) wireless terminals. Dedicated Systems Magazine, 2001.
[78] Cheng-Wei Chen, Chung-Lin Tang, Young-Chia Lin, and Jenq-Kuen Lee.
ORC2DSP: Compiler infrastructure supports for VLIW DSP processors. In Pro-
ceedings of International Symposium on VLSI Design, Automation and Test,
2005.
[79] Chung-Ju Wu, Sheng-Yuan Chen, and Jenq Kuen Lee. Copy propagation op-
timizations for VLIW DSP processors with distributed register files,. In Pro-
ceedings of International Workshop on Languages and Compilers for Paral lel
Computing (LCPC 2006), 2006.
[80] Radhika Thekkath and Susan J. Eggers. The effectiveness of multiple hardware
contexts. In In Sixth International Conference on Architectural Support for Pro-
gramming Languages and Operating Systems, pages 328–337, 1994.
[81] Anant Agarwal, Beng hong Lim, David Kranz, and John Kubiatowicz. April: A
processor architecture for multiprocessing. In In Proceedings of the 17th Annual
International Symposium on Computer Architecture, pages 104–114, 1990.
[82] Jeffrey S. Snyder, David B. Whalley, and Theodore P. Baker. Fast context
switches: Compiler and architectural support for preemptive scheduling. Micro-
processors and Microsystems, 19:35–42, 1995.
[83] Chuck Thacker, Ed McCreight, Butler Lampson, Robert Sproull, and David
Boggs. Alto: A personal computer. Computer Structures: Principles and Exam-
ples, pages 549–572, 1981.
[84] Burton J. Smith. Architecture and applications of the hep multiprocessor com-
puter system. In Proceedings of SPIE, volume 298, pages 241–148, 1981.
[85] Robert A Iannucci. Toward a dataflow/von neumann hybrid architecture.
SIGARCH Comput. Archit. News, 16(2):131–140, 1988.
[86] Wolf Dietrich Weber and Ashish Gupta. Exploring the benefits of multiple hard-
ware contexts in a multiprocessor architecture: preliminary results. SIGARCH
Comput. Archit. News, 17(3):273–280, 1989.
BIBLIOGRAPHY 119
[87] Peter R. Nuth and William J. Dally. A mechanism for efficient context switching.
In ICCD ’91: Proceedings of the 1991 IEEE International Conference on Com-
puter Design on VLSI in Computer & Processors, pages 301–304, Washington,
DC, USA, 1991. IEEE Computer Society.
[88] Vijayaraghavan Soundarara jan and Anant Agarwal. Dribbling registers: A mech-
anism for reducing context switch latency in large-scale multiprocessors. Tech-
nical report, 1992.
[89] B. Zolfaghari. A dynamic scheduling algorithm with minimum context switches
for spacecraft avionics systems. In Proceedins of 2004 IEEE Aerospace Confer-
ence, volume 4, pages 2618–2624, 2004.
[90] Inki Hong, Miodrag Potkonjak, and Marios Papaefthymiou. Efficient block
scheduling to minimize context switching time for programmable embedded pro-
cessors. Design Automation for Embedded Systems, 4(4):311–327, 1999.
[91] Volker Barthelmann. Inter-task register-allocation for static operating systems.
In LCTES/SCOPES ’02: Proceedings of the joint conference on Languages, com-
pilers and tools for embedded systems, pages 149–154, New York, NY, USA, 2002.
ACM.
[92] Robert V. Binder. Testing Object-Oriented Systems: Models, Patterns, and
Tools. Addison-Wesley Professional, 1999.
[93] Justin E. Forrester and Barton P. Miller. An empirical study of the robust-
ness of windows nt applications using random testing. In Proceedings of the 4th
conference on USENIX Windows Systems Symposium, pages 59–68, 2000.
[94] Robert M. Hierons and Mercedes G. Merayo. Mutation testing from probabilis-
tic finite state machines. In Proceedings of the Testing: Academic and Industrial
Conference Practice and Research Techniques - MUTATION (TAICPARTMU-
TATION 2007), pages 141–150, 2007.
[95] Srinivas Bangalore and Giuseppe Riccardi. Stochastic finite-state models for spo-
ken language machine translation. In Proceedings of the NAACL-ANLPWorkshop
on Embedded Machine Translation Systems, pages 52–59, 2000.
[96] Erik L. L. Sonnhammer, Gunnar von Heijne, and Anders Krogh. A hidden
markov model for predicting transmembrane helices in protein sequences. In Pro-
ceedings of the Sixth International Conference on Intel ligent Systems for Molec-
ular Biology (ISMB), pages 175–182, 1998.
BIBLIOGRAPHY 120
[97] L. R. Rabiner and B. H. Juang. An introduction to hidden markov models. IEEE
ASSP Magazine, 3(1):4–16, January 1986.
[98] IEEE Standard. IEEE Standard POSIX 1003.1c-1995 thread extensions. IEEE,
1995. ISO/IEC 9945-1:1996.