以廣義網路流為基礎之低功率可程式邏輯閘陣列記憶體映射演算法

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研究生：	許天騵 Tien-Yuan Hsu
論文名稱：	以廣義網路流為基礎之低功率可程式邏輯閘陣列記憶體映射演算法 A Generalized Network Flow Based Algorithm for Power-Aware FPGA Memory Mapping
指導教授：	王廷基 Ting-Chi Wang
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 資訊工程學系 Computer Science
論文出版年：	2007
畢業學年度：	95
語文別：	英文
論文頁數：	21
中文關鍵詞：	廣義網路流、低功率、可程式邏輯閘陣列、記憶體映射
外文關鍵詞：	Generalized Network Flow, Power-Aware, FPGA, Memory Mapping
相關次數：	點閱：2 下載：0
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在可程式邏輯閘陣列上，裝置上的實體記憶體是很重要的一個部份，它可以實作設計者所設計的各種記憶體結構。由於實體記憶體的廣泛使用，起動這些實體記憶體所耗費的能量成為了整體動態耗電量的相當重要的一部份。在這一篇論文裡，我們提出了一個低功率記憶體映射的演算法，在考慮記憶體數量的限制之下，將邏輯記憶體映射到實體記憶體上。我們的方法將記憶體映射的問題轉換成一個廣義網路流的問題，它可以同時將實體記憶體資源分配給邏輯記憶體，而不是將邏輯記憶體一個接著一個地做資源分配的工作；在和另一個已存在的方法比較之後，可以展示出我們的方法是比較優秀的，在問題有解的情況之下，我們一定可以找到一個耗電量最少的最佳解，這是另一個已存在的方法做不到的。

Embedded memory blocks in FPGAs allow designers to implement a variety of memory structures. With the increasing use of embedded memory blocks, the power consumed by them has formed a significant part of the total dynamic power consumption. In this thesis, we present a power-aware memory mapping algorithm, which maps user-defined logical memories to physical embedded memory blocks under the memory resource constraint. Our algorithm converts the memory mapping problem to a generalized network flow (GNF) problem, which can distribute embedded memory blocks to all logical memories at the same time. Our algorithm is compared with an existing method, and the promising experimental results show that our algorithm can always efficiently generate optimal solutions while the existing method cannot.

Abstract (in Chinese)    II
Abstract    III
Contents    IV
List of Figures    V
List of Tables    VI

Chapter 1. Introduction    1
Chapter 2. Problem Formulation    5
Chapter 3. Related Work    7
Chapter 4. A Generalized Network Flow Based Algorithm    9
4.1. Our GNF model    10
4.2. Optimality proof    14
4.3. Speed-up techniques    16
Chapter 5. Experimental Results    18
Chapter 6. Conclusions    20
References    21

Fig. 1: A 512x4 logical memory is mapping based on configuration 512x1    2
Fig. 2: A 512x4 logical memory is mapping based on configuration 128x4..    3
Fig. 3: GNF model for memory mapping, where L, U, C, and G denote flow lower bound, flow upper bound, cost, and gain factor, respectively.    11
Fig. 4: Network example, where the box on the right shows the lower bound, upper bound, cost, and gain factor respectively for each arc..    13
Fig. 5: A min-cost flow, where the box on the right shows the flow, cost, and gain factor respectively for each arc..    13
Fig. 6: New network after reducing the arcs and nodes, where the box on the right shows the lower bound, upper bound, cost, and gain factor respectively for each arc...    17

TABLE I: Block demands and power consumptions for all configurations.    8
TABLE II: Experimental results for 30 designs.    19

                                

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[6] Altera Corporation, Stratix II Device Handbook vol.2, August 2006.
[7] Xilinx Corporation, Virtex-4 User Guide, April, 2007.
[8] Altera Corporation, Achieving Low Power in 65-nm Cyclone III FPGAs, March, 2007.
[9] Mentor Graphics Corporation, FPGA Resource Management, January, 2007.
[10] Altera corporation, Quartus II Handbook, May, 2007.
[11] M. R. Garey and D. S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness, W. H. Freeman, San Francisco, 1979.
[12] R. K. Ahuja, T. L. Magnanti, and J. B. Orlin, Network flows Theory, Algorithms, and Applications, Prentice-Hall International, 1993.
[13] P. A. Jensen, Operations Research Models and Methods. Available: http://www.me.utexas.edu/~jensen/ORMM/

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