低密度奇偶檢查碼(LDPC codes)在瀑布區(water-fall region)有著良好的性能，但是錯誤平層(error-floor)現象總是將低密度奇偶檢查碼排除在許多通訊系統和儲存設備之外。
這現象是低密度奇偶檢查碼的Tanner圖的某些結構所造成，那會讓訊息傳遞解碼器(message-passing decoder)無法輸出正確的碼字(codeword)。
對於儲存系統而言，需要的是高碼率低密度奇偶檢查碼和高吞吐量。
我們提出一個只需要一點額外的疊代次數便可以降低高碼率低密度奇偶檢查碼錯誤平層的技術。
除此之外，此技術也被設計成只需要耗費額外的一點硬體資源。
若是解碼失敗,根據最後一次疊代的不滿足檢查節點(check-nodes)，一定有一些錯誤位元在與他們相連接的變數節點(variable-nodes)之中。
結合了支配的陷阱組合(trapping-set)資訊，可能錯誤的位元數量可以被大幅地減少，甚至能夠直接利用查找表(LUT)找到錯誤位元。
提出的技術是針對可能錯誤的位元去指派修正的後驗機率(a posteriori probability)然後將他們送回解碼器去重新執行解碼。
這個方法有著適當的計算量和資料儲存量，並且能夠達到一個很好的錯誤平層性能。
(9216, 8352)和(18816, 16800)分別碼率為0.906和0.892-不規則高碼率準循環低密度奇偶檢查碼被使用來展示所提出的解碼器在重要性抽樣(importance sampling)的模擬中能夠降低錯誤平層好幾個層級。
並且在(9216, 8352)-分層架構解碼器的硬體實現結果下顯示降低錯誤平層組件只需要增加少許的邏輯閘數量。

Low-density parity-check (LDPC) codes have great performance in water-fall region, but the error-floor phenomenon always excludes LDPC codes from many communication and storage systems.
The phenomenon is resulted from some structures in LDPC codes' Tanner graph that disable the message-passing decoders to output correct codewords.
For storage systems, high-rate LDPC codes and high-throughput are required.
A technique is proposed to lower the error-floors of high-rate QC-LDPC codes with only a few extra number of iterations.
In addition, the technique is also devised to cost only a few extra hardware resources.
If a decoding failure happens, based on the unsatisfied check-nodes in the last iteration , it is known that there must be some error-bits in their adjacent variable-nodes.
Combined with dominant trapping-set information, the amount of error-likely bits can be substantially reduced, even find the error-bits directly by look-up table (LUT).
The proposed lowering technique aims at error-likely bits or error-bits to assign modified a posteriori probability (APP) to and send them back to a decoder to re-perform decoding process.
This manner has a moderate quantity of computation and data storage, and could achieve a great error-floor performance.
The (9216, 8352) and (18816, 16800)-irregular high-rate Quasi-Cyclic LDPC (QC-LDPC) code that have a coderate 0.906 and 0.892 have been used to demonstrate the proposed decoder can lower the error-floor by several orders in importance sampling simulations.
And the result of hardware implementation in (9216, 8352)-layered decoding shows that the added gatecount of the error-floor lowering module is just a little.

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