由於嵌入式裝置通常都需要仰賴電池供應電源, 所以“省電”在嵌入式系統的領域向來是個重要的議題。 隨著製程的進步,嵌入式系統已經進階使用多處理器系統晶片(MPSoC), 進而提供更好的處理效能。 然而,這亦導致晶片耗能(power consumption)大幅提升,縮短電池使用的時間。 因此,如果能夠在設計的階段有效地知道耗能的資訊,可以幫助設計者找出系統耗能點(power bottleneck),進而改善以延長電池使用時間。 在本論文中我們實作一個針對多核心架構的硬體模組,可以收集更多方面的硬體事件, 如:處理器、主記憶體和匯流排相關的硬體事件,在搭配已知的功耗模型,來偵測應用程式的耗能情形,這個硬體模組能夠一起於硬體模擬平台上運行, 所以不但有完整的系統模擬且可以快速地得到耗能量測的結果。

Advances in IC technologies have enabled embedded systems to use multi-processor system-on-chip (MPSOC) to meet the increasing performance demands. Since power is critical in mobile embedded systems, such as mobile phones, GPS navigation systems, digital cameras, and handheld DVD players, it is important to understand how power is consumed at the design stage of MPSOC-based embedded systems. Then, the power bottleneck of the design may be identified and improved for prolonged battery operations. In this thesis, we present a system-wide power estimation system for designing MPSOC-based embedded systems. This system can collect and accumulate hardware events of different system components, such as CPU, BUS, and memory, and then by coupling with related system power models, report the power consumption of application software. This system can be integrated into FPGA-based MPSOC design for fast power and performance evaluations. We will demonstrate the implementation of the system and show how it helps to collect power profile of an MPSOC system design.

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