在互補式金氧半元件中，降低源/汲極寄生電阻是很重要的課題，金屬化之蕭特基能障源/汲極，被認為是極具潛力的一項技術。但蕭特基接面具有獨特的載子傳輸機制，可以藉由摻雜析離層的加入，來調整蕭特基能障，增加電流並降低雙極性導通的電洞電流。因為蕭特基能障源/汲極的採用，可在低電壓下產生強烈的熱電子效應，蕭特基能障被應用於電荷捕捉式快閃記憶體元件中。本論文利用二維元件模擬，深入探討本質與具摻雜析離層之蕭特基能障電荷捕捉式快閃記憶體其讀取、寫入、抹除操作下的不同機制，並詳細分析在寫入時蕭特基能障與儲存電荷間的耦合影響。
摻雜析離層對載子傳輸與注入的機制具有關鍵的影響。使用摻雜析離層，除增加汲極端電子電流並降低雙極性導通的電洞電流外，同時亦減弱了源極的蕭特基電子能障，縮小了橫向電場，讓靠近源極的熱電子寫入能力減低；而在負偏壓時，由於電洞導通電流的減小，也造成了電洞抹除能力的降低。依據載子注入能力，可將具摻雜析離層之蕭特基能障快閃記憶體分為兩類：其一為類似本質蕭特基之低濃度摻雜析離層元件，其次為類似傳統摻雜接面之高濃度摻雜析離層元件。類似本質蕭特基之低濃度摻雜析離層元件擁有較佳的寫入與抹除的效率，並具較好的短通道效應；但較低的汲極電流限制了元件讀取的速度。而類似傳統摻雜接面之高濃度摻雜析離層元件則呈向相反之特性，代表了具摻雜析離層之蕭特基能障電荷捕捉式快閃記憶體在設計參數時，必須在寫入/抹除，與讀取能力之間做取捨，尤其當元件不斷微縮後。若基於微縮性與低功率操作，不具摻雜析離層的本質之蕭特基能障電荷捕捉式快閃記憶體應較具應用優勢。
利用多次的數值疊代與元件模擬，可精確地分析在寫入時蕭特基能障與儲存電荷間的耦合影響。研究顯示，電子傳導與注入能力，都與源極之蕭特基能障息息相關。當電子被捕捉於缺陷層中時，其電荷分佈與大小會改變通道橫向電場的分佈與大小，除了降低電場的極值外，同時也讓注入的區域遠離源極與通道的接面處，使得儲存電荷的分佈比預期中更為廣泛。然而，由於蕭特基能障具有獨特的源極注入特性，能擁有較好的多位元分辨能力，採用蕭特基能障源/汲極，依然極有益於多位元儲存的電荷捕捉式快閃記憶體元件。

Metallic Schottky barrier source/drain has been intensively studied because of their potentiality to minimize parasitic source/drain resistance in CMOS technologies. The Schottky barrier devices generate particular carriers transport associated with the Schottky barrier junctions. Dopant-segregated (DS) technique was widely adopted to tailor Schottky barrier junctions, increasing on-state current and suppressing ambipolar conduction. Because Schottky barrier junctions can produce a strong enhancement of hot-carrier generation to ensure a large gate current at low voltages, the Schottky barrier source/drain is used in nonvolatile charge-trapping memory cells to exhibit unique source-side electron programming and drain-side hole erasing. This dissertation elucidates the differences of physical mechanisms between the DS-structured and non-DS Schottky barrier charge-trapping cells and discusses the coupling of Schottky barriers and trapped charges involved in cell programming and reading. Two-dimensional device simulations were employed to investigate the cell conduction, programming, and erasing.
Since the DS layer tailors the effective Schottky barrier height in Schottky barrier devices, the DS condition has a key function in determining the injected mechanisms and locations of cell programming and erasing. It narrows the source-side Schottky electron barrier to minimize the source-side lateral field, thereby reducing the source-side electron programming. It also decreases the drain-side hole erasing because of the reduced hole drain current and drain-side lateral field. Based on the injected mechanisms, two categories of DS-structured cells are classified: 1) light DS Schottky barrier-like cell and 2) heavy DS conventional-like cell. The Schottky barrier-like cells exhibit enhanced programming/erasing characteristics with better short-channel effects, whereas they generate low electron drain currents for cell reading. The tradeoffs inherent in the cell programming/erasing, the short-channel effect, and the cell reading necessitate optimizing the DS profiles in scaled Schottky barrier charge-trapping cells. Based on cell scalability and low-power operation, the intrinsic Schottky barrier source/drain should be the most appropriate in NOR-type charge-trapping cells to ensure efficient programming/erasing.
Using numerical iterations, this thesis precisely examines the coupling of Schottky barriers and trapped charges involved in cell programming and two-bit/cell reading. In the Schottky barrier cells, both the conduction and injection of electron carriers depend on the Schottky source barrier lowering. The local trapped charges counteract the gate-controlled field, reducing the programming efficiency, and moving the subsequent injections away from the source edge. The distribution of total trapped-charges is considerably wider than that of the initial injection. Because of source-side conduction, the excellent screening of second bit effect in the Schottky barrier cells is beneficial to operate the NOR-type multi-bit/cell charge-trapping memories.

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