暫存器轉移層次(register transfer level)普遍地被使用在積體電路(integrated circuit)的設計。從暫存器轉移層次裡，我們可以更清楚地和更有效率地獲得硬體結構和資料流向(dataflow)。高級層次(high level)的資訊能使用在邏輯閘層次(gate level)的路徑選擇(path selection)，所以我們能更有效率地選擇路徑。

在這篇論文中，我們提出一個從暫存器轉移層次的電路中提取限制(constraint)條件的方法。限制條件包含了控制訊號、埠(port)的名字、暫存器的名字，以及資料路徑上的訊號，這些將會決定電路的運作情形。從每個暫存器轉移層次的控制流向圖(control flow graph)，我們選取了控制流向路徑(control flow path)並且取得了每條控制流向路徑的控制訊號。然後，我們再根據每條控制流向路徑取得資料流向的內容。根據我們從暫存器轉移層次提取出的限制條件，我們使用在邏輯閘層次的路徑選擇上。路徑選擇工具根據限制條件選擇出的路徑是功能上需要被測試的路徑。實驗結果顯示出每個電路的特性，根據電路和它們的限制條件，我們能觀察到每個電路的路徑差異性。功能上需要被測試的路徑佔電路所有路徑的百分之七十∼百分之九十幾。

Register transfer level (RTL) is commonly used for a integrated circuit (IC) design. We can
obtain the hardware structure and dataflow more clearly and efficiently from RTL. The high-level
information can be used for a path selection at the gate level, so we can select paths more efficiently.
In this thesis, we propose a method to extract constraints form register transfer level circuits.
The constraints include control signals, port names, register names and data-path signals which
determine the operation of circuits. We select control flow paths from the control flow graph
(CFG) of each RTL circuit and get the control signals for each control flow path. Then, we get the
dataflow according to each control flow path. According to the constraints extracted from RTL, we
use them for a path selection tool at the gate level. The paths selected by the path selection tool
according to the constraints are functionally needed to be tested. The experimental results show
that the characteristics of circuits, so we can observe the differences of paths according to their
circuits and constraints. The percentage of the paths functionally needed to be tested is 70% ˜ 90%
in the circuits.

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