在三維晶片裡傳輸電源電壓所用的『穿矽連接孔』(Through Silicon Via)當中，一旦有任何原因造成其損壞，則可能會使該條穿矽連接孔所對應到附近區域的電源電壓品質有所下降，特別在電路運作當中工作負載較大時，會產生無預警的電源電壓突波，造成電源電壓發生大幅下降，最後甚至影響到電路操作的主要功能。為了確保電路在運作時的可靠度，我們希望能提前檢測出這些受到損壞的電源電壓傳輸用之穿矽連接孔，也因為這個動機，先前已經提出了許多種利用『環形振盪器』(Ring-Oscillator)當作感測元件，並且以此為基礎進行晶片內部即時『電源電壓落差』(VDD-drop)的監測方法。然而，這些監測晶片內部電源電壓落差的方法並沒有特別考慮到晶片本身在工作時，內部的溫度會隨時間而有所改變，而這些溫度改變的效應則可能會影響到電壓預測的準確性。因此在本篇論文當中，我們提出了一種可以考慮晶片內部溫度效應的影響下，電源電壓傳輸用之穿矽連接孔的測試方法。這個創新的測試方法中包含了以下的特色，首先，我們提出了一個可以校準環形振盪器本身受到製程飄移影響的方法，減少因製程飄移因素所造成電源電壓預測的誤差；另外，我們提出了一個考慮晶片內部溫度效應並且可以針對某段監測期間內，最嚴重的電源電壓落差情況之電壓預測方法。藉由這些方法來提升我們在判斷電源電壓傳輸用之穿矽連接孔的品質是否及格的準確性。

A latent defect in a power-delivery TSV in a 3D IC could cause power glitches under a heavy workload in the field and thereby leading to timing failure. In order to catch these defects before they actually strike, on-line ring-oscillator based VDD-drop monitoring schemes have been proposed previously. However, these methods have not taken into account the effect of the temperature, which could affect their accuracy in the final VDD prediction. In this thesis, we present a temperature-aware test method for power-delivery TSVs, with several features - including a process-calibration scheme and a temperature-aware worst-case VDD prediction scheme. Based on the these schemes, the pass-or-fail decision on the quality of a power-TSV can be made more accurately.

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