研究生: |
徐信豪 Hsin-Hao Hsu |
---|---|
論文名稱: |
MOHOS結構之電容與電晶體在記憶體上的應用與電性分析 Electrical Characterization of Metal-Oxide-High-k dielectric-Oxide-Semiconductor(MOHOS) Capacitors and Transistors for Memory Applications |
指導教授: |
李雅明
Joseph Ya-Min Lee |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering |
論文出版年: | 2006 |
畢業學年度: | 94 |
語文別: | 中文 |
論文頁數: | 99 |
中文關鍵詞: | MOHOS 、非揮發性記憶體 |
相關次數: | 點閱:3 下載:0 |
分享至: |
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
我們已經研究金屬-氧化物-高介電係數介電層-氧化物-矽結構(MOHOS-type flash memory) 並使用HfO2 和Dy2O3 作為高介電係數介電層結構的電容器和電晶體。並對元件作基本的電性量測與可靠度分析;首先藉由不同的儲存層材料的差異,探討其對MOHOS元件電特性的影響;再來探討不同RTA溫度對儲存層特性的影響。
由MOHOS電容結構的量測結果,在J-V curve的測量上,使用HfO2當作電荷儲存層的樣品在10V的外加電壓下RTA 600℃時有最小的漏電流密度大小為10-6 A/cm2;而使用Dy2O3當作電荷儲存層的樣品在10V的外加電壓下RTA 400℃有最小的漏電流大小密度為10-8 A/cm2。
由MOHOS電晶體結構的結果,在基本電性上的表現,如:ID-VD,ID-VG及C-V等,皆證明電晶體能夠正常的操作,使用Dy2O3材料當作電荷儲存層的樣品,在基本電晶體電性方面其次臨界斜率為St=104.2 mV/dec、遷移率為276 cm2/V-sec,在記憶體特性方面其寫入速度為+12V經過10 ms能夠有1.1V的Vth差、I-V memory window大小為1.85V、retention time為2x108秒(6年)。
Abstract
Conventional SONOS (polysilicon-oxide-nitride-oxide-silicon) non-volatile memory devices use silicon nitride as the charge storage layer. In this work, metal–oxide–high-k dielectric–oxide–silicon (MOHOS) capacitors and transistors are fabricated using HfO2 and Dy2O3 high-k dielectrics as the charge storage layer. The Al/SiO2/Dy2O3/SiO2/Si capacitors have a C-V memory window of 1.88V. The leakage current density of the Al/SiO2/Dy2O3/SiO2/Si capacitor is 10-8A/cm2 at 10V. The leakage current density of the Al/SiO2/HfO2/SiO2/Si capacitor is 10-6/cm2 at 10V. The leakage current density of the Al/SiO2/Dy2O3/SiO2/Si capacitor is lower than that of Al/SiO2/HfO2/SiO2/Si capacitor at the same bias voltage.
The programming speed of Al/SiO2/Dy2O3/SiO2/Si transistor is characterized by a Vth shift of 1.1V with a programming stress pulse voltage of 12V for 10 ms. After a +12V, 0.1 s program pulse and a -12V, 0.5 s erase pulse, the Al/SiO2/Dy2O3/SiO2/Si transistors can keep a ΔVth window of 0.5V for 2x108 seconds. The corresponding numbers for Al/SiO2/HfO2/SiO2/Si transistors are 100 ms and 2x104 seconds. The better performance of the Al/SiO2/Dy2O3/SiO2/Si transistors is attributed to the larger conduction band offset at the Dy2O3/SiO2 interface (2.3eV) versus 1.6eV at the HfO2/SiO2 interface.
References
[1] D. Kahng and S. M. Sze, “A floating gate and its application to memory devices,” IEEE Trans. Electron Devices, vol. 14, no. 9, pp.629-629, 1967.
[2] D. Frohman-Bentchkowsky, “A fully decoded 2048-bit electrically programmable MOS-ROM,” IEEE ISSCC Dig. Tech. Papers, pp. 80-81, 1971.
[3] H. A. R. Wegener, A. J. Lincoln, H. C. Pao, M. R. O’Connell, and R.E. Oleksiak, “The variable threshold transistor, a new electrically alterable, non-destructive read-only storage device,” IEDM Tech. Dig., 1967.
[4] W. J. Tsai, N. K. Zous, C. J. Liu, C. C. Liu, C. H. Chen, T. Wang, S. Pan, C. Y. Lu, and S.H. Gu, “Data retention behavior of a SONOS type two-bit storage flash memory cell,” IEDM Tech. Dig., pp. 32.6.1 -32.6.4., 2001.
[5] T. Sugizaki, M. Kobayashi, M. Ishidao, H. Minakaca, M. Yamaguchi, Y. Tamura, Y. Sugiyama, T. Nakanishi, and H. Tanaka, “Novel multi-bit SONOS type flash memory using a high-K charge trapping layer,” IEEE Symp. VLSI Technology Digest of Technical, pp. 24-28, 2003.
[6] C. T. Swift, G. L. Chindalore, K. Harber, T. S. Harp, A. Hoefler, C. M. Hong, P. A. Ingersoll, C. B. Li, E. J. Prinz, and J. A. Yater, “An embedded 90nm SONOS nonvolatile memory utilizing hot electron programming and uniform tunnel erase,” IEDM Tech. Dig., pp. 927-930, 2002.
[7] S. Tiwari, F. Rana, H. Hanafi, A. Hartstein, E. F. Crabbe, and K. Chan, “A silicon nanocrystals based memory,” Appl. Phys. Lett., vol. 68, no. 10, pp. 1377-1379, 1996.
[8] Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal nanocrystal memories—Part I: Device design and fabrication,” IEEE Trans. Electron Devices, vol. 49, no. 9, pp. 1606-1613, 2002.
[9] Y. N. Tan, W. K. Chim, B. J. Cho, and W. K. Choi, ”Over-erase phenomenon in SONOS-type flash memory and its minimization using a hafnium oxide charge storage layer,” IEEE Trans. Electron Devices, vol. 51, no. 7, pp. 1143-1147, 2004.
[10] B. Jiankang and M. H. White, “Design considerations in scaled SONOS nonvolatile memory devices,” Solid-State Electron., vol. 45, pp. 113–120, 2001.
[11] H. Wann and C. Hu, “High endurance ultrathin tunnel oxide in MONOS device structure for dynamic memory applications,” IEEE Electron Device Lett., vol. 16, pp. 491–493, 1995.
[12] Y. Kamagaki, S. I. Minami, T. Hagiwara, K. Furusawa, T. Furuno, K. Uchida, M. Terasawa, and K. Yamazaki, “Yield and reliability of MNOS EEPROM products,” IEEE J. Solid-State Circuits, vol. 24, pp. 1714–1722, 1989.
[13] M. H. White, D. A. Adams, and B. Jiankang, “On the go with SONOS,” IEEE Circuits Devices Mag., vol. 16, pp. 22–31, 2000.
[14] W. D. Brown and J. E. Brewer, Eds., Nonvolatile semiconductor memory technology, a comprehensive guide to understanding and using NVSM devices. New York: IEEE Press, pp. 193–309, 1998.
[15] Yamada, Y. Hiwa, T. Tamane, K. Amemiya, Y. Ohshima, and K. Yoshikawa, ”Degradation mechanism of flash EEPROM program after program/erase cycles,” IEDM Tech. Dig., pp. 23-26, 1993.
[16] W. J. Tsai, N. K. Zous, C. J. Liu, C. C. Liu, C. H. Chen, T. Wang, S. Pan, C. Y. Lu, and S. H. Gu, ”Data retention behavior of a SONOS type two-bit storage flash memory cell”, IEDM Tech. Dig., pp. 719-722, 2001.
[17] B. Jiankangand and M. H. White, “Effects of two-step high temperature deuterium anneals on SONOS nonvolatile memory devices”, IEEE Electron Device Lett., vol. 22, no. 1, pp. 17 -19, 2001.
[18] S. M. Sze, Physics of Semiconductor Device, 2nd ed., Wiley, New York, 1981.
[19] J. R. Yeargan and H. L. Taylor, “The Poole-Frenkel effect with compensation present,” J. Appl. Phys. vol. 39, no. 12, pp. 5600-5604 , 1968.
[20] W. J. Zhu, T. P. Ma, T. Tamagawa, J. Kim, and Y. Di, “Current transport in metal/hafnium oxide/silicon structure,” IEEE Electron Device Lett., vol. 23, no. 2, pp. 97-99, 2002.
[21] D.K. Schroder, “Semiconductor material and device characteristics,” Wiley, Arizona, 1998.
[22] M. Lenzlinger and E. H. Snow, “Fowler-Nordheim tunneling into thermally grown SiO2,” J. Appl. Phys., vol. 40, no. 1, pp. 278-283, 1969.
[23] B. Hankang and M. H. While, “Retention reliability enhanced SONOS NVSM with scaled programming voltage,” IEEE Aerospace Conference Proceedings, vol. 5, pp. 2383-2390, 2002.
[24] M. French, H. Sathianathan, and M. White, “A SONOS nonvolatile memory cell for semiconductor disk application,” IEEE Nonvolatile Memory Technology Review, pp. 70-73, 1993.
[25] M. S. Joo, B. J. Cho, C. C. Yeo, D. S. H. Chan, S. J. Whoang, S. Matthew, L. K. Bera, N. Bala, and D. L. Kwong, “Formation of hafnium-aluminum-oxide gate dielectric using single cocktail liquid source in MOCVD process,” IEEE Trans. Electron Devices, vol. 50, no. 10, pp. 2088-2094, 2003.
[26] S. Zafar, A. Callegari, E. Gusev, and M. V. Fischetti, “Charge trapping related threshold voltage instabilities in high permittivity gate dielectric stacks,” J. Appl. Phys., vol. 93, no. 11, pp. 9298-9300, 2003.
[27] Y. N. Tan, W. K. Chim, W. K. Choi, M. S. Joo, and B. J. Cho, “Hafnium aluminum oxide as charge storage and blocking-oxide layer in SONOS-type nonvolatile memory for high-speed operation,” IEEE Trans. Electron Devices, vol. 53, no. 4, pp. 654-661, 2006.
[28] W. J. Tsai, N. K. Zous, C. J. Liu, C. C. Liu, C. H. Chen, T. Wang, S. Pan, C. Y. Lu, and S. H. Gu, “Data retention behavior of a SONOS type two-bit storage flash memory cell, ” IEDM Tech. Dig., pp. 719-722, 2001.
[29] 李豪捷,化學乾式蝕刻及N2O氣體退火對SONOS快閃記憶體元件的影響,國立清華大學碩士論文,民國九十二年六月.