能夠順利畢業，我第一個想感謝的是吳誠文老師。我在實驗室裡做的每項研究，老師都很有耐心地一遍又一遍指導我不足的地方，包括對事情的思考、判斷方式以及技術上的觀念等等。除了研究，在表達和待人接物上我也從老師身上學到許多。每次開會時，老師的指導都讓我感覺醍醐灌頂，也每次都讓我意識到還有很大的空間需要學習以及加強。在投稿論文的時候，老師雖然行程十分忙碌，卻仍然排開空檔、犧牲假日時間，一字一句、不厭其煩地幫忙更正語意以及內容，甚至因為截稿時間的關係，在晚餐時間餓著肚子、幫忙修改論文到最後一刻，此舉讓學生真的非常感動。老師待人溫厚，對學生的關懷都像對自己家人一樣，讓我見識到像老師這樣有成就的人，處事的出發點時時刻刻都是為了關懷、為了別人。
我第二個想感謝的人是李旻昇學長，在我剛進實驗室的時候，李旻昇學長的租屋處離學校很近，我常常和學長一起吃飯，討論研究和未來的打算。這樣的頻繁討論使我對專業知識有困惑時，都能在第一時間找的到專家詢問。每次在研究上有所進展時，學長總是不吝於給予鼓勵，讓我充滿信心、並對研究充滿興趣。另外，我想感謝和我同屆的周盈妏和吳姿欣在修課以及生活上給予的鼓勵及幫助。雖然已經過了好幾年，我仍然時時懷念起我們一起籌備活動、一起出遊的那些歡樂時光。我也想感謝台積電合作計畫的夥伴們。在我的碩博士生涯裡，台積電的夥伴們提供了許多寶貴的資料以及真實待解的問題，讓我們得以發揮、並試圖解決業界所面臨的真實問題，這個機會真的十分難得，讓我分外珍惜。
我特別想感謝的是讓我無後顧之憂、得以專心完成學業且疼愛我的爸媽，兩位姊姊，祖父母、外公外婆、舅舅，以及其他家人們。是家人們的支持，我才一直有信心和信念、完成學位。在接下來的日子裡，我將懷著感恩的心情，繼續與家人一起分擔、分憂、分享生活的大小事。最後，感謝我周遭所有的朋友們，是你們的鼓勵以及包容，才讓我得以順利完成論文，謝謝你們。

Memories have been considered as one of the major drivers of CMOS technology, due to their high density, high capacity, critical timing, sensitivity, etc. Memory diagnosis is therefore important for technology and product development. In memory diagnosis, memory test data need to be collected and analyzed. However, as memory density and capacity continue to grow, the amount of test data also keeps increasing, making it difficult to extract useful information for further diagnosis and analysis. In this thesis, we propose a test data compression technique, which compresses the fail bitmaps into different failure formats, resulting in more compact storage and faster access in the future. Experimental results show that for memories with different failure distributions, the failure bitmaps can be compressed to 21.03-57.26% of their original size without information loss.
For memory diagnosis, memory failure pattern identification is traditionally considered as a key task to speed up the memory diagnosis and failure analysis process. A memory failure pattern is defined as a topological distribution of fail bits in the memory array. The critical memory failure patterns (those are found frequently, so are the yield killers), however, may change in different memory designs and process technologies. It is difficult to consider all critical failure patterns beforehand as they are not be defined in advance. To solve this problem, we propose a memory failure pattern identification system, which can identify critical memory failure patterns from a large amount of memory failure bitmaps automatically, even if they are not defined in advance. In our experiment for 132,488 4-Mb memory failure bitmaps, the proposed failure pattern identification system can automatically identify 6 critical yet undefined failure patterns in minutes, in addition to all known patterns. In comparison, the state-of-the-art commercial tools need manual inspection of the memory failure bitmaps to identify the same failure patterns.
Another approach to improve the memory yield is redundancy repair, which uses redundancy to repair (replace) faulty parts of memories. To ensure high repair efficiency and final product yield, it is necessary to explore and develop memory redundancy architectures carefully. However, due to different memory failure distributions and design constraints of memory architectures, it is difficult to explore the efficiency of different redundancy architectures thoroughly. To solve this problem, we propose Raisin-C, which can be used to simulate the repair rates of different memory redundancy architectures with 2D and 3D redundancy constraints. In our experiments, the repair rates of 10 different 3D redundancy architectures with 3 different redundancy analysis algorithms in a given failure pattern distribution are simulated. The experimental result shows that the difference of the repair rates between the most efficient and least efficient memory redundancy architectures is up to 49.42%.
In addition, to improve the stack yield of channel-based 3D DRAM, in this thesis, we introduce two redundancy schemes, i.e., Cubical Redundancy Architecture 1 and 2 (CRA1 and CRA2) [1], and propose two 3D redundancy schemes, i.e., Configurable Cubical Redundancy Architecture 1 and 2 (CoCRA1 and CoCRA2). The difference between CRAs and CoCRAs is that the spare memory of CoCRAs is configurable to allow efficient repair of row, column, and cluster failures, while that of CRAs only has one type of spare configuration. In (Co)CRA1, the global spares that can be shared across dies are associated with each DRAM die as conventional DRAMs. In (Co)CRA2, we use an SRAM on the logic die as global spares, which have higher flexibility than CoCRA1. The experimental result shows that CoCRA1 can achieve 28.09% higher stack yield than the traditional redundancy architecture, with only 50% of its spare space. There is only 0.05% and 0.2% area overhead on the logic die and DRAM die, respectively. On the other hand, CoCRA2 can further improve the stack yield to almost 100%, but with 2.3 times higher area overhead than CoCRA1.

[1] W.-T. Chiang and C.-W. Wu, "3D Redundancy Architecture for Wide-I/O DRAM," Master Thesis, Dept. Electr. Eng., National Tsing Hua University, 2012.
[2] L.-T. Wang, C.-W. Wu, and X. Wen, Design for Testability: VLSI Test Principles and Architectures. San Francisco, CA: Elsevier (Morgan Kaufmann), 2006.
[3] K.-L. Cheng, C.-W. Wang, J.-N. Lee, Y.-F. Chou, C.-T. Huang, and C.-W. Wu, "FAME: a fault-pattern based memory failure analysis framework", in Proc. IEEE/ACM Int. Conf. on Comput.-Aided Des. (ICCAD), pp. 595–598, Nov. 2003.
[4] B.-Y. Lin, M. Lee, C.-W. Wu, "A memory failure pattern analyzer for memory diagnosis and repair," in Proc. IEEE VLSI Test Symp. (VTS), pp. 234–239, Apr. 2012.
[5] J.-F. Li and C.-W. Wu, "Memory fault diagnosis by syndrome compression," in Proc. Int. Conf. Des., Aut., and Test in Eur. (DATE), pp. 97–101, Mar. 2001.
[6] C.-F. Wu, C.-T. Huang, and C.-W. Wu, "RAMSES: a Fast Memory Fault Simulator," in Proc. IEEE Int Symp. Def. and Fault Tol. VLSI Syst. (DFT), pp. 165–173, Nov. 1999.
[7] A. J. van de Goor, Testing Semiconductor Memories: Theory and Practice. Chichester, England: John Wiley & Sons, 1991.
[8] C.-F. Wu, C.-T. Huang, K.-L. Cheng, and Cheng-Wen Wu, "Fault simulation and test algorithm generation for random access memories," IEEE Trans. Comput.-Aided Des. Int. Circu. Syst., vol. 21, no. 4, pp. 480–490, Apr. 2002.
[9] V. N. Yarmolik, S. Hellebrand, and H. Wunderlich, “Self-adjusting output data compression: An efficient BIST technique for RAMs,” in Proc. Conf. Des., Aut., Test Eur. (DATE), pp. 173–179, Feb. 1998.
[10] S. Hellebrand, H. Wunderlich, A. Ivaniuk, Y. Klimets, and V. N. Yarmolik, “Error detecting refreshment for embedded DRAMs,” in Proc. IEEE VLSI Test Symp. (VTS), pp. 384–390, Apr. 1999.
[11] S. Hellebrand, H. Wunderlich, A. Ivaniuk, Y. Klimets, and V. N. Yarmolik, “Efficient online and offline testing of embedded DRAMs,” IEEE Trans. Comp., vol. 51, no. 7, pp. 801–809, Jul. 2002.
[12] J.-F. Li, R.-S. Tzeng, and C.-W. Wu, “Diagnostic data compression techniques for embedded memories with built-in self-test,” J. Electr. Test.: Theory Appl., vol. 18, no. 4–5, pp. 515–527, Aug.–Oct. 2002.
[13] J. T. Chen, J. Rajski, J. Khare, 0. Kebichi, and W. Maly, “Enabling embedded memory diagnosis via test response compression”, in Proc. IEEE VLSI Test Symp. (VTS), pp. 292–298, Apr. 2001.
[14] J. T. Chen, J. Khare, K. Walker, S. Shaikh, J. Rajski, and W. Maly, “Test response compression and bitmap encoding for embedded memories in manufacturing process monitoring,” in Proc. Int. Test Conf. (ITC), pp. 258–267, Oct. 2001.
[15] R.-F. Huang, C.-L. Su, C.-W. Wu, Y.-J. Chang, and W.-C. Wu, “A memory built-in self-diagnosis design with syndrome compression,” in Proc. IEEE Int. Workshop Curr. Def. Based Test. (DBT), pp. 97–102, Apr. 2004.
[16] R.-F. Huang, C.-L. Su, C.-W. Wu, S.-T. Lin, K.-L. Luo, and Y.-J. Chang, “Fail pattern identification for memory built-in self-repair,” in Proc. IEEE Asian Test Symp. (ATS), pp. 366–371, Nov. 2004.
[17] C.-L. Su, R.-F. Huang, C.-W. Wu, K. –L. Luo, and W.-C. Wu, "A Built-in Self-Diagnosis and Repair Design With Fail Pattern Identification for Memories," IEEE Trans. Very Large Scale Int. (VLSI) Syst., vol. 19, no. 12, pp. 2184–2194, Dec. 2011.
[18] N. Mukherjee, A. Pogiel, J. Rajski, and J. Tyszer, “High volume diagnosis in memory BIST based on compressed failure data,” IEEE Trans. Comput.-Aided Des. Int. Circu. Syst., vol. 29, no. 3, pp. 441–453, Mar. 2010.
[19] Z. Song, "SRAM failure analysis evolution driven by technology scaling," in Proc. IEEE Int. Symp. Phys. and Failure Analysis of Int. Circu., pp. 223–230, June-July 2014.
[20] J. Vollrath, U. Lederer, and T. Hladschik, "Compressed bit fail maps for memory fail pattern classification," in Proc. IEEE Euro. Test Workshop (ETW), pp. 125–130, May, 2000.
[21] C.-W. Wang, K.-L. Cheng, J.-N. Lee, Y.-F. Chou, C.-T. Huang, C.-W. Wu, F. Huang, and H.-T. Yang, "Fault pattern oriented defect diagnosis for memories," in Proc. Int. Test Conf. (ITC), pp. 29–38, Sept. 2003.
[22] J. Li, Y. Huang, W.-T. Cheng, C. Schuermyer, D. Xiang, E. Faehn, and R. Farrugia, "A Hybrid Flow for Memory Failure Bitmap Classification," in Proc. IEEE Asian Test Symp. (ATS), pp. 314–319, Nov. 2012.
[23] M. A. Merino, S. Cruceta, A. Garcia, and M. Recio, "SmartBitTM: bitmap to defect correlation software for yield improvement," in Proc. IEEE/SEMI Adv. Sem. Man. Conf. and Workshop, pp. 194–198, Sept. 2000.
[24] J. Segal, A. Jee, D. Lepejian, and B. Chu, "Using electrical bitmap results from embedded memory to enhance yield," IEEE Des. & Test Comput., vol. 15, no. 3, pp. 28–39, May 2001.
[25] R. David and A. Fuentes, "Fault diagnosis of RAMs from random testing experiments," IEEE Trans. Comput., vol. 39, no. 2, pp. 220–229, Feb. 1990.
[26] D. Niggemeyer and E. M. Rudnick, "Automatic generation of diagnostic memory tests based on fault decomposition and output tracing," IEEE Trans. Comput., vol. 53, no. 9, pp.1134–1146, Sept. 2004.
[27] S. M. Al-Harbi, F. Noor, and F. M. Al-Turjman, "March DSS: A New Diagnostic March Test for All Memory Simple Static Faults," IEEE Trans. Comput.-Aided Des. Int. Circu. Syst., vol. 26, no. 9, pp. 1713–1720, Sept. 2007.
[28] B. B. Sindahl, “Interactive graphical analysis of bit-fail map data using interactive pattern recognition,” in Proc. Int. Test Conf. (ITC), pp. 687–695, 1987.
[29] P. Mazumder and J. K. Patel, “Parallel testing for pattern-sensitive faults in semiconductor random-access memories,’’ IEEE Trans. Comput., vol. 38, no. 3, pp. 394–407, Mar. 1989.
[30] T. Viacroze and M. Lequeux, “Analysis of failures on memories using expert system techniques,” in Proc. Int. Test Conf. (ITC), pp. 823–932, Sept. 1990.
[31] Y. Baltagi, D. L. Rosi, V. Tancorre, C. Garagnon, E. Faehn, M. Barone, D. Appello, C. Suzor, "Embedded memory fail analysis for production yield enhancement," in Proc. Annual IEEE/SEMI Adv. Sem. Man. Conf., pp. 1–5, May 2011.
[32] Y. Zorian, "Embedded infrastructure IP for SOC yield improvement," in Proc. IEEE/ACM Des. Aut. Conf. (DAC), pp. 709–712, June 2002.
[33] L. Milor, "A Survey of Yield Modeling and Yield Enhancement Methods," IEEE Tran. Sem. Man., vol. 26, no. 2, pp. 196–213, May 2013.
[34] R.-F. Huang, Y.-F. Chou, and C.-W. Wu, "Defect oriented fault analysis for SRAM," in Proc. IEEE Asian Test Symp. (ATS), pp. 256–261, 2003.
[35] R. S. Collica, J. P. Card, and W. Martin, "SRAM bitmap shape recognition and sorting using neural networks," IEEE Trans. Sem. Man., vol. 8, no. 3, pp. 326–332, Aug. 1995.
[36] P. Dubey, A. Garg, and S. K. Bhaskarani, "Built in defect prognosis for embedded memories," in Proc. IEEE Des. and Diagn. of Electr. Circu. Syst., pp. 1–6, Apr. 2007.
[37] P. Jacob, A. Zia, O. Erdogan, P. M. Belemjian, J.-W. Kim, M. Chu, R. P. Kraft, J. F. McDonald, and K. Bernstein, “Mitigating memory wall effects in high-clock-rate and multicore CMOS 3-D processor memory stacks,” in Proc. IEEE, vol. 97, no. 1, pp. 108–122, Jan. 2009.
[38] S. Borkar, “3-Dintegration for energy efficient system design,” in Proc. IEEE/ACM Des. Aut. Conf. (DAC), pp. 214–219, Jun. 2011.
[39] U. Kang, H.-J. Chung, S. Heo, S.-H. Ahn, H. Lee, S.-H. Cha, J. Ahn, D. Kwon, J. H. Kim, J.-W. Lee, H.-S. Joo, W.-S. Kim, H.-K. Kim, E.-M. Lee, S.-R. Kim, K.-H. Ma, D.-H. Jang, N.-S. Kim, M.-S. Choi, S.-J. Oh, J.-B. Lee, T.-K. Jung, J.-H. Yoo, and C. Kim, “8 Gb 3-D DDR3 DRAM using through-silicon-via technology,” IEEE J. Sol.-State Circu., vol. 45, no. 1, pp. 111–119, Jan. 2010.
[40] T. Sekiguchi, K. Ono, A. Kotabe, and Y. Yanagawa, “1-Tbyte/s 1-Gbit DRAM architecture using 3-D interconnect for high-throughput computing,” IEEE J. Sol.-State Circu., vol. 46, no. 4, pp. 828–837, Apr. 2011.
[41] J.-S.Kim, C. S. Oh,H. Lee,D. Lee,H.-R. Hwang, S. Hwang, B. Na, J. Moon, J.-G. Kim, H. Park, J.-W. Ryu, K. Park, S.-K. Kang, S.-Y. Kim, H. Kim, J.-M. Bang, H. Cho, M. Jang, C. Han, J.-B. Lee, K. Kyung, J.-S. Choi, and Y.-H. Jun, “A 1.2 V 12.8 GB/s 2 Gb mobile wide-I/O DRAM with 4 x 128 I/Os using TSV-based stacking,” in Proc. IEEE Int. Sol.-State Circu. Conf. Dig. Techn. Pap. (ISSCC), pp. 496–498, Feb. 2011.
[42] R. S. Patti, “Three-dimensional integrated circuits and the future of system-on-chip designs,” in Proc. IEEE, vol. 94, no. 6, pp. 1214–1224, June 2006.
[43] K. Puttaswamy and G. Loh, “3D-Integrated SRAM Components for High-Performance Microprocessors,” IEEE Trans. Comput., vol. 58, no. 10, pp. 1369 –1381, June 2009.
[44] H. Saito, M. Nakajima, T. Okamoto, Y. Yamada, A. Ohuchi, N. Iguchi, T. Sakamoto, K. Yamaguchi, and M. Mizuno, “A chip-stacked memory for on-chip SRAM-rich SoCs and processors,” IEEE J. Sol.-State Circu., vol. 45, no. 1, pp. 15–22, Jan. 2010.
[45] M. B. Healy, K. Athikulwongse, R. Goel, M. M. Hossain, D. H. Kim, Y.-J. Lee, D. L. Lewis, T.-W. Lin, C. Liu, M. Jung, B. Ouellette, M. Pathak, H. Sane, G. Shen, D. H. Woo, X. Zhao, G. H. Loh, H.-H. S. Lee, and S.K. Lim, “Design and analysis of 3d-maps: A many-core 3d processor with stacked memory,” in Proc. IEEE Cust. Int. Circu. Conf. (CICC), pp. 1–4, Sept. 2010.
[46] P. Jacob, O. Erdogan, A. Zia, P. M. Belemjian, R. P. Kraft, and J. F. McDonald, “Predicting the performance of a 3D processor-memory chip stack,” IEEE Des. and Test Comput., vol. 22, no. 6, pp. 540–547, 2005.
[47] P. Garrou, C. Bower, and P. Ramm, Handbook of 3D Integration: Technology and Applications of 3D Integrated Circuits vol. 2, 2008.
[48] C.-W. Chou, Y.-J. Huang, and J.-F. Li, "Yield-enhancement techniques for 3D random access memories," in Proc. Int. Symp. VLSI Des. Aut. Test (VLSI-DAT), pp. 104–107, 2010.
[49] L. Jiang, R. Ye, and Q. Xu, "Yield enhancement for 3D-stacked memory by redundancy sharing across dies," in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des. (ICCAD), pp. 230–234, Nov. 2010.
[50] X. Wang, D. Vasudevan, and H.-H. S. Lee, "Global Built-In Self-Repair for 3-D Memories with Redundancy Sharing and Parallel Testing," in Proc. IEEE Int. 3D Syst. Int. Conf. (3DIC), pp. 1–8, Feb. 2012.
[51] M. Taouil and S. Hamdioui, "Layer Redundancy Based Yield Improvement for 3D Wafer-to-Wafer Stacked Memories," in Proc. IEEE Eur. Test Symp. (ETS), pp. 45–50, May 2011.
[52] Y.-F. Chou, D.-M. Kwai, and C.-W. Wu, "Yield Enhancement by Bad-Die Recycling and Stacking With Though-Silicon Vias," IEEE Trans. Very Large Scale Int. (VLSI) Syst.,vol. 19, pp. 1346–1356, June 2011.
[53] S.-K. Lu, C.-L. Yang, Y.-C. Hsiao, and C.-W. Wu, "Efficient BISR Techniques for Embedded Memories Considering Cluster Faults," IEEE Trans. Very Large Scale Int. (VLSI) Syst., vol. 18, pp. 184–193, Feb. 2010.
[54] M. Lee, L.-M. Denq, and C.-W. Wu, "A Memory Built-In Self-Repair Scheme Based on Configurable Spares," IEEE Trans. Comput.-Aided Des. Int. Circu. Syst., vol. 30, pp. 919–929, 2011.
[55] R.-F. Huang, J.-F.-Li, J.-C. Yeh, and C.-W. Wu, "Raisin: Redundancy Analysis Algorithm Simulation," IEEE Des. & Test Comput., vol. 24, May–June 2007.
[56] C.-H. Lin, C.-L. Su, M.-S. Lee, and C.-W. Wu, "Evaluation of Redundancy Analysis Schemes for Reparable Memories with Redundancy Constraints," in VLSI Test Techn. Workshop (VTTW), 2008.
[57] E. J. Marinissen, and Y. Zorian, “Testing 3D chips containing through-silicon vias,” in Proc. IEEE Int. Test Conf. (ITC), pp. 1–11, Nov. 2009.
[58] Wide I/O Single Data Rate (JEDEC Standard JESD229), JEDEC Solid State Technology Association, Dec. 2011. [Online]. Available: http://www.jedec.org/standards-documents/docs/jesd229.
[59] B.-Y. Lin, W.-T. Chiang, C.-W. Wu, M. Lee, H.-C. Lin, C.-N. Peng, and M.-J. Wang, "Redundancy Architectures for Channel-Based 3D DRAM Yield Improvement," in Proc. IEEE Int. Test Conf. (ITC), pp. 1–7, Oct. 2014.
[60] C. H. Stapper, “Simulation of spatial fault distributions for integrated circuit yield estimations,” IEEE Trans. Comput.-Aided Des. Int. Circu. Syst., vol. 8, no. 12, pp. 1314–1318, Dec. 1989.
[61] W.-H. Wang and C.-W. Wu, "Statistical Analysis for Failure-Pattern Based Memory Failure Diagnostics," Master Thesis, Dept. Electr. Eng., National Tsing Hua University, 2007.
[62] J. L. Bentley and T. Ottmann, "Algorithms for reporting and counting geometric intersections," IEEE Trans. Comput., vol. C-28, no. 9, pp. 643–647, Sept. 1979.
[63] Concurrent_unordered_set class provided by Threading Building Blocks (TBB). [Online]. Available: https://www.threadingbuildingblocks.org/docs/help/reference/containers_overview/concurrent_unordered_set_cls.htm.
[64] P.-Y. Chen, T.-H. Wu, M. Lee, C.-W. Wu, B.-Y. Lin, C.-H. Tien, H.-C Lin, H. Chen, C.-N. Peng, and M.-J. Wang, “A Memory Yield Improvement Scheme Combining Built-In Self-Repair and Error-Correction Codes,” in Proc. IEEE Int. Test Conf. (ITC), pp. 1–9, Nov. 2012.
[65] C.-T. Huang, C.-F. Wu, J.-F. Li, and C.-W. Wu, "Built-In Redundancy Analysis for Memory Yield Improvement," IEEE Trans. Rel., vol. 52, pp. 386–399, Dec. 2003.
[66] J.-S. Kim, C. S. Oh, H. Lee, D. Lee, H. R. Hwang, S. Hwang, B. Na, J.Moon, J.-G.Kim,H. Park, J.-W. Ryu,K. Park, S. K. Kang, S.-Y. Kim, H. Kim, J.-M. Bang, H. Cho, M. Jang, C. Han, J.-B. Lee, J.-S. Choi, and Y.-H. Jun, “A 1.2 V 12.8 GB/s 2 Gb mobile wide-I/O DRAM with 4 128 I/Os using TSV based stacking,” IEEE J. Sol.-State Circu., vol. 47, no. 1, pp. 107–116, Jan. 2012.
[67] J. Jeddeloh and B. Keeth, “Hybrid memory cube: New DRAM architecture increases density and performance,” in Proc. Symp. VLSI Techn. (VLSIT), pp. 87–88, Jun. 2012.
[68] R. Goering, "MemCon Panel: Promises and Pitfalls of 3D-IC Memory Standards," Aug. 2013 [Online]. Available: http://www.cadence.com /Community/blogs/ii/archive/2013/08/11/memcon-panel-promises-and-pitfalls-of-3d-ic-memory-standards.aspx.
[69] Y.-F. Chou, D.-M. Kwai, M.-D. Shieh, and C.-W. Wu, "Reactivation of spares for off-chip memory repair after die stacking in a 3-D IC with TSVs," IEEE Trans. Circu. Syst., vol. 60, no. 9, pp. 2343–2351, Sep. 2013.
[70] V. Schober, S. Paul, and O. Picot, “Memory built-in self-repair using redundant words,” in Proc. IEEE Int. Test Conf. (ITC), pp. 995–1001, Oct.–Nov. 2001.
[71] J.-F. Li, J.-C. Yeh, R.-F. Huang, and C.-W. Wu, "A built-in self-repair design for RAMs with 2-D redundancy," IEEE Trans. Very Large Scale Int. (VLSI) Syst., vol. 13, pp. 742–745, Jun. 2005.
[72] T. Kawagoe, J. Ohtani, M. Niiro, T. Ooishi, M. Hamada, and H. Hidaka, "A Built-In Self-Repair Analyzer (CRESTA) for Embedded DRAMs," in Proc. Int. Test Conf. (ITC), pp. 567–574, Oct. 2000.
[73] X. Du, S. M. Reddy, W.-T. Cheng, J. Rayhawk, and N. Mukherjee, "At-speed Built-in Self-repair Analyzer for Embedded Word-oriented Memories," in Proc. Int. Conf. VLSI Des., pp. 895–900, 2004.
[74] C.-T. Huang, J.-R. Huang, C.-F. Wu, C.-W. Wu, and T.-Y. Chang, "A Programmable BIST Core for Embedded DRAM," IEEE Des. & Test Comput., vol. 16, no. 1, pp. 59–70, Jan.–Mar. 1999.
[75] H.-C. Shih, P.-W. Luo, J.-C. Yeh, S.-Y. Lin, D.-M. Kwai, S.-L. Lu, A. Schaefer, and C.-W. Wu, "DArT: A Component-Based DRAM Area, Power, and Timing Modeling Tool," IEEE Trans. Comput.-Aided Des. Int. Circu. Syst., vol. 33, no. 9, pp. 1356–1369, Sept. 2014.