隨著資訊與科技的進步，高速傳輸的應用與日俱增。有限的通道頻寬與不理想效應將造成資料在傳送時有符際干擾(Inter-symbol Interfer-ence, ISI)的現象，使資料在接收端判決上錯誤率提升，難以辨識正確的訊號。因此能補償通道損失的等化器在高速傳輸中扮演重要的角色。

本論文提出一個操作在每秒六十億位元(6Gps)的四階振幅脈衝調變發射機，其中包含混合式驅動級所組成的三階前饋式等化器以及提供時脈訊號的數位式鎖相迴路。此發射機使用真實單相時脈 D 型正反器將輸入訊號做統整，並利用二選一數據多工器調整前饋式等化器補償通道損失之係數大小，使發射機可依照通道的不同調整為最適合的補償係數。前饋式等化器前級使用四選一數據多工器，使進入驅動級前的操作速度為 750MHz，節省功耗與面積消耗。而前饋式等化器使用混合式驅動級取代傳統電流式和電壓式驅動級，將傳統電流式與電壓式驅動級之優點保留，並透過分割驅動級，達到可調式等化器的作用；由此設計出一個能操作在高速且具有良好線性度與更大輸出振幅的可調式前饋式等化器。
而發射機電路操作必定需要一個時脈訊號，本論文使用操作在拾五億赫茲
(1.5GHz)數位式鎖相迴路來供應發射機所需之時脈訊號，其中電路架構由相位頻率檢測器、加入兩個運算放大器以解決不理想效應的電荷泵、迴路濾波器、壓控振盪器和除頻器組成；壓控振盪器運用切換式電容層降低單一頻帶壓控振盪器的增益來提升相位雜訊的表現。在此數位式鎖相迴路輸出的時脈訊號後級接上四相位時脈產生器，最後提供發射機所需之四相位且頻率為七億五千萬赫茲(750MHz)的時脈訊號。
本論文使用台積電(TSMC) 0.65nm 1P9M 的 CMOS 製程實現，供應電壓為
1.2V，實現一個操作在每秒六十億位元(6Gps)的四階振幅脈衝調變發射機，其中輸出振幅為 1.506V，位準分離失配率為 98.8%；數位式鎖相迴路參考突波值為-85.34dBc，整體發射機功耗消耗為 275mW。

With the progress of information technology, the application of high-speed transmission is increasing day by day. However, the limitation bandwidth of the channel and undesirable effect will cause the inter-symbol interference (ISI) during data communication, so that the data error rate on the receiver will increase, and it is more difficult to identify the correct signal. Therefore, the equalizer which can compensate for the channel loss plays an important role in high-speed transmission.

In this thesis, it presents an operating at 6Gps 4-level pulse-amplitude modulation (PAM-4) transmitter. Which includes a 3-taps feed-forward equalizer composed of hybrid PAM-4 drivers and digital phase-locked loop providing clock source. The transmitter uses true single phase clock D-flip flop (TSPC DFF) to organize input signal, and uses two to one multiplexer (2：1 mux) to adjust the coefficient of feed-forward equalizer with compensate channel loss, which makes the transmitter could be used in different types of channel by adjusted to the most suitable compensation coefficients. The previous stage of feed-forward equalizer uses four to one multiplexer (4：1 mux), which makes the operating speed could be 750MHz before entering the drivers. Because of the lower operating speed, it can reduce the power and the area consumption. Moreover, the structure of feed-forward equalizer composes of hybrids PAM-4 drivers instead of conventional current-mode or voltage-mode drivers. What is more, hybrids PAM-4 drivers retain the advantages of conventional current-mode and voltage-mode drivers, and to make the equalizer adjustable through dividing the drivers. Depending on these design, the feed-forward equalizer can operate at high speed, then perform good linearity and larger output swing.

However, the transmitter must operate with a clock source, so this thesis uses an operating at 1.5GHz digital phase-locked loop to supply a clock signal for transmitter. In addition, the structure of PLL consist of phase frequency detector, charge pump with two operational amplifier to solve non-ideal effects, loop filter, voltage controlled oscillator, frequency divider. The voltage controlled oscillator by using the capacitor bank to keep the gain down of single-band voltage controlled oscillator in order to improve the performance of phase noise. Then at the output of digital PLL is connected to four phase clock generator, which is to provide the transmitter with a four phase and oscillate at 750MHz clock source.
In conclusion, the 6Gb/s PAM-4 Transmitter with 3-Tap Hybrid Feed-Forward Equalizer and 1.5 GHz Digital Phase-locked Loop was fabricated in the TSMC 65nm CMOS process with a supply voltage of 1.2V. The output amplitude of this transmitter is 1.506V, and Ratio of Level Mismatch (RLM) is about 98.8%. The reference spur of digital PLL is -85.34dBc. The Power consumption of this transmitter is 275mW.

[1] Matteo Bassi, Francesco Radice, Melchiorre Bruccoleri, Simone Erba, and Andrea Mazzanti, " A High-Swing 45 Gb/s Hybrid Voltage and Current-Mode PAM-4 Transmitter in 28 nm CMOS FDSOI, " IEEE Journal of Solid-State Circuits, vol. 51, Issue: 11, Nov. 2016.
[2] Pen-Jui Peng, Yan-Ting Chen, Sheng-Tsung Lai, and Hsiang-En Huang, " A 112-Gb/s PAM-4 Voltage-Mode Transmitter With Four-Tap Two-Step FFE and Automatic Phase Alignment Techniques in 40-nm CMOS, " IEEE Journal of Solid-State Circuits, vol. 56, Issue: 7, July 2021.
[3] Xuqiang Zheng, Hao Ding; Feng Zhao, Danyu Wu, Lei Zhou, Jin Wu, Fangxu Lv, Jianye Wang, and Xinyu Liu, " A 50–112-Gb/s PAM-4 Transmitter With a Fractional-Spaced FFE in 65-nm CMOS, " IEEE Journal of Solid-State Circuits, vol. 55, Issue: 7, July 2020.
[4] R. Farjad-Rad, C.-K.K. Yang, and M.A. Horowitz, " A 0.3-/spl mu/m CMOS 8-Gb/s 4-PAM serial link transceiver, " IEEE Journal of Solid-State Circuits, vol. 35,Issue: 5, May 2000.
[5] Srikanth Gondi, and Behzad Razavi, " Equalization and Clock and Data Recovery Techniques for 10-Gb/s CMOS Serial-Link Receivers, "IEEE Journal of Solid-State Circuits, vol. 42, Issue: 9, Sept. 2000.
[6] Ankur Agrawal, John Bulzacchelli, Timothy Dickson, Yong Liu, Jose Tierno, and Daniel Friedman, " A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOS, " IEEE Journal of Solid-State Circuits, vol. 47, Issue: 12, Dec. 2012.
94
[7] Seungho Han, Sooeun Lee, Minsoo Choi, Jae-Yoon Sim, Hong-June Park, and Byungsub Kim, " A Coefficient-Error-Robust Feed-Forward Equalizing Transmitter for Eye-Variation and Power Improvement, " IEEE Journal of Solid-State Circuits, vol. 51, Issue: 8, Aug. 2016.
[8] Diego Fabian Tondo, and Ramiro Rogelio Lopez, " A Low-Power, High-Speed CMOS/CML 16:1 Serializer, " 2009 Argentine School of Micro-Nanoelectronics, Technology and Applications.
[9] Dengjie Wang, Hong Chen, Wenhuan Luan, Xin Lin, Fangxu Lv, Ziqiang Wang, Hanjun Jiang, Chun Zhang, and Zhihua Wa, " A 4-40 Gb/s PAM-4 transmitter with a hybrid driver in 65 nm CMOS technology, "2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS).
[10] A. Homayoun ,and Behzad Razavi, "Analysis of Phase Noise in Phase/Frequency Detectors," IEEE Trans. on Circuits and Systems-I: regular papers, vol.60, no. 3 pp. 529-539, March. 2013.
[11] M.S. Hwang , J. Kim ,and D.-K. Jeong, " Reduction of pump current mismatch in charge-pump PLL," Electronics Letters, Vol.45, pp.135-136, Jan. 2009.
[12] N. H. E. Weste and D. Harris, CMOS VLSI design : a circuits and systems perspective. Boston: Pearson/Addison-Wesley, 2010
[13] Byungho Min ,and Samuel Palermo, " A 20Gb/s triple-mode (PAM-2, PAM4,and duobinary) transmitter, 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS)
[14] 高曜煌,《射頻鎖相迴路 IC 設計》, 滄海書局, 2017
[15] 劉深淵, 楊清淵, 《鎖相迴路》, 滄海書局, 2017
[16] Behzad Razavi, Design of analog CMOS integrated circuits, 2001