本論文是詳細地敘述一個應用在LCD平面顯示器中，把紅綠藍三原色信號轉換成低電壓低雜訊的差動信號傳輸介面（LVDS）。我們使用TSMC 0.35 1P4M CMOS製程技術，由國科會晶片設計中心下線製作。晶片內有一個鎖相迴路提供的時脈，將晶片內外時脈的相位與頻率鎖定以消除其時間上的延遲，並兼有頻率合成器的功能，可以將內部的時脈倍頻以供信號取樣時使用。我們把8 bits（紅、綠或藍色）的輸入信號轉換成低電壓低雜訊的差動信號後，最終會整合到一數位類比轉換器內，進而利用這高速的數位類比轉換器將資料轉換到一LCD的驅動電路，提供平面顯示器的全彩畫面。
內建的鎖向迴路工作電壓是3.3伏特，操作頻率介於20MHz到128MHz，以符合VGA（640×480）、SVGA（800×600）、XGA（1024×768）、甚至SXGA（1280×1024）等不同平面顯示器解析度的應用。我們的LVDS驅動器與接收器將來會被一起應用在個人電腦或工作站（繪圖控制晶片）與平面顯示器（驅動電路）之間的傳輸媒介。透過此LVDS傳輸介面可使得紅綠藍三原色的信號能快速有效率地從一端傳送到另一端，減少成本與資料傳輸的損耗。

CIC下線送回的晶片，經量測之後達到一些預計的效能，包括內建的鎖向迴路、數位邏輯電路、以及LVDS輸出級三部分。在量測時必須特別注意輸出輸入的寄生效應，使用的印刷電路板線路也必須特別留意，因為極容易導致信號的失真或錯誤。

關鍵字：平面顯示器、傳輸介面、差動信號、鎖向迴路

A Low-Voltage-Differential-Signaling transmitter is implemented in TSMC 0.35 1P4M CMOS process to convert 8 bits of CMOS/TTL data into one LVDS data stream. A phase-locked transmit clock is transmitted in parallel with the data stream over a second LVDS link. During every cycle of the transmit clock, 8 bits of input data are sampled and transmitted. If, for example, a transmit clock frequency of 128MHz (XGA mode can be achieved) is chosen, 8 bits of R/G/B data will be transmitted at a rate of 1Gbps.
A PLL embedded is used as a transmit clock that operates under 3.3V of power supplies and at an input frequency range between 20MHz and 128MHz. Thus the LVDS transmitter may be employed in VGA, SVGA, XGA, and SXGA display mode applications. This LVDS transmitter together with a LVDS receiver will be placed between a host graphics controller and a LCD panel controller. The RGB signals from a PC or workstation will be transmitted over the LVDS link and then into a LCD driver.

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