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研究生： 劉晉硯
Liu, Jinn-Yann
論文名稱： 應用於脈衝雷達系統晶片之時序控制電路-可程式寬可調區間相位移動器
A Programmable Wide-range Phase Shifter for the Timing Control of Pulsed Radar SoC
指導教授： 黃錫瑜
Huang, Shi-Yu
口試委員: 黃錫瑜
Shi-Yu Huang
李鎮宜
Chen-Yi Lee
洪浩喬
Hao-Chiao Hong
朱大舜
Ta-Shun Chu
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2014
畢業學年度： 102
語文別： 中文
論文頁數： 36
中文關鍵詞： 雷達晶片 、相位移動 、時間延遲 、可調延遲元件 、延遲鎖相迴路 、鎖相迴路
外文關鍵詞： radar, phase shifter, time delay, tunable delay element, delay-locked loop, phase-locked loop
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    • 摘要
    隨著半導體製程與CMOS技術的進步，雷達系統現今已被廣泛應用在許多電子產品中，例如：「雷達式的肺部病患心肺分析系統」，或是「雷達式的防嬰兒窒息之睡眠監控系統」等等。其中，脈衝式的雷達會以定期的方式發射連續的脈衝訊號，並藉由其反射回音來檢測搜尋範圍內的物件。藉由觀測此回音訊號所花費的時間，可以得到物體所在的位置資訊。因此，對一個脈衝式的雷達系統晶片來說，內建的【時序控制】單元是非常重要的一個環節，因為它將會直接影響包括方向和距離在內的測量準確度。此篇論文主要即是專注在設計一雷達系統當中的時序控制單元。在這篇報告中，我們將介紹一個我們在此計畫中所開發的寬可調區間的【可程式相位移動器電路】。這個電路可以將兩個 10MHz 時脈訊號中的其中之一，往前移動一個可控制的相位量 (概念上相近於一段時間差)。這個相對量可大可小，範圍包含了整個週期訊號區間。我們所設計的這個電路具有許多特點，包括 (1) 它具有寬達 100ns 的可調區間，(2) 它幾乎是由標準元件庫細胞所組成，非常容易進行製程的轉移。(3) 利用倍頻/除頻的方式，產生微小相位移動的製程校正方法。在此篇論文的最後，有此電路的下線量測結果，並且附上缺失改進的方法與模擬結果，以及未來的設計目標。

    Abstract
    With the progress of technology and CMOS process, radar system is widely used in many of today’s electronic devices. A pulsed radar would transmit continuous pulse signals periodically, and detect the object by receiving the echo signals. By the transmit time of the echo signal it takes, radar system yield the position information of the object. Therefore, a timing control unit is very important part for a pulsed radar SoC, since it would directly affect the measurement accuracy including direction and distance. In this work, we would introduce a wide-range Programmable Phase Shifter. This circuit can create a programmable phase shift (i.e. timing delay in other words) to a given 10MHz clock signal. The circuit is designed with following features: (1) The tunable range of phase shift as wide as 100ns. (2) All Digital design and almost implemented by digital standard cells, easy to transport to another process. (3) A calibration scheme using frequency multiplier/divider to get a fine shifted phase.

    Content Abstract i 摘要 ii 誌謝 iii Content iv List of Figures vi List of Tables viii Chapter 1 Introduction 1 1.1 Introduction 1 1.2 Thesis Organization 5 Chapter 2 Architecture and Operation 6 2.1 Overview 6 2.2 Operations 10 Chapter 3 Circuit Design and Simulation Results 14 3.1 All-Digital Phase-Locked Loop (ADPLL) 14 3.2 An Integer-N Frequency Divider 16 3.3 Delay-Locked Loop (DLL) 18 3.4 Tunable Delay Element (TDE) 20 3.5 Coarse-tuning Block 22 3.6 Simulation Result 23 Chapter 4 Measurement Result 24 4.1 Chip Layout and Die Photo 24 4.2 Measurement Environment 26 4.3 Measurement Report 28 Chapter 5 Conclusion 32 Chapter 6 Recommendation and Future Plan 33 Bibliography 35   List of Figures Fig. 1-1: The timing diagram of programmable phase shifter 3 Fig. 2-1: The block diagram of Programmable Phase Shifter. 7 Fig. 2-2: The detail block diagram of Programmable Phase Shifter. 7 Fig. 2-3: The timing diagram to illustrate cyclic property 9 Fig. 2-4: Illustration of coarse-tuning mechanism. 11 Fig. 2-5: The matching layout of tri-state buffers (g1 and g2) 12 Fig. 2-6: The timing diagram of coarse-fine approach 12 Fig. 2-7: Summary of four operational modes. 13 Fig. 3-1: The post-layout simulated characteristics of ADPLL. 15 Fig. 3-2: Illustration of the timing diagrams of the frequency divider 17 Fig. 3-3: The period table of calibration clocks. 17 Fig. 3-4: (a) The block diagram of Delay-Locked Loop (DLL) (b) The timing diagram of DLL. 18 Fig. 3-5: Two Step searching mechanism for DLL locking. 19 Fig. 3-6: The architecture of TDE 20 Fig. 3-7: The counters in coarse-tuning block. 22 Fig. 3-8: The simulated timing diagram of Programmable Phase Shifter 23 Fig. 4-1: The layout of Programmable Phase Shifter 25 Fig. 4-2: The chip photo of Direct-Sampling Impulse Radar 25 Fig. 4-3: Circuit Measure Environment 26 Fig. 4-4: The timing diagram of the scope 27 Fig. 4-5: 10 cases of the measured timing waveform 28 Fig. 4-6: Phase shift amount vs. input control code. 29 Fig. 4-7: The DNL and INL analysis 30 Fig. 4-8: Jitter measurement report 31 Fig. 6-1: Simulated waveform of Φfast (a) before and (b) after improvement. 33 Fig. 6-2: Modified coarse-tuning phase error simulation 34   List of Tables Table 3-1: The post-layout characteristics of TDE 21 Table 4-1: The approximated area of different processes. 24 Table 4-2: Summary of measurement result. 30 Table 4-3: The comparison characteristic table 31  

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