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研究生: 陳柏荔
PO-LI CHEN
論文名稱: 應用於電子構裝冷卻之各類型冷板最佳化設計
Thermal Optimal Design for Compact Cold Plates in Electronics Cooling Applications
指導教授: 洪英輝
YING-HUEI HUNG
口試委員:
學位類別: 博士
Doctor
系所名稱: 工學院 - 動力機械工程學系
Department of Power Mechanical Engineering
論文出版年: 2007
畢業學年度: 95
語文別: 中文
論文頁數: 492
中文關鍵詞: 最佳化設計冷板電子構裝冷卻
外文關鍵詞: Thermal Optimal Design, Compact Cold Plates, Electronics Cooling
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  • 本論文研究首先應用有效的熱網路數值分析方法,針對離散二維/三維電子構裝鑲嵌於多層結構板未結合或結合各類型冷板的熱傳與流體流動摩擦特性,作一系列的理論分析,並將計算之熱流結果與前人之理論解析解及實驗數據相比較,皆相當吻合;進而,在研究中亦針對影響上述散熱結構組合之熱流特性的相關參數做有系統的探討。
    另外,針對離散二維/三維電子構裝鑲嵌於多層結構板結合各類型冷板設計,本研究更成功地提出一完整且有系統的最佳化設計方法。此最佳化設計方法乃結合反應曲面法及序列二次規劃法,可使設計者有效且快速地在多個限制條件下找出最佳化的散熱設計。在設計過程中,首先利用工程統計分析所作出的敏感度測試可定量地分析出系統中各相關影響參數之貢獻度;接著應用反應曲面法搭配實驗計劃法來求得滿足其熱流特性之二階迴歸曲面關係式;最後再藉由數值最佳化方法來有效地求出在各種限制條件下的最佳化散熱設計。在本研究中,成功地將前述之最佳化設計方法及流程應用於中央處理器冷卻及多層印刷電路板冷卻之各類型冷板最佳化設計之研究上。
    以前述之理論模式結合最佳化設計方法及流程為基礎,研究中更進一步的成功開發出二套應用於中央處理器冷卻以及應用於多層印刷電路板冷卻之各類型冷板的電腦輔助最佳化設計系統。系統中包括人機介面操作相當友善的前置處理器、根據所發展之理論模式而建立的散熱分析器、具有自動建立實驗設計、建構迴歸曲面以及預測最佳設計等功能的最佳化運算器、應用多媒體互動技術的後置處理器、執行軟體過程中親和的使用者介面、以及相關的材料及熱流特性資料庫。最後,本研究成功地應用自行開發出之電腦輔助最佳化設計系統於多限制條件下之離散二維/三維電子構裝鑲嵌於多層結構板結合各類型冷板最佳化設計上,其結果皆驗證此電腦輔助最佳化設計系統的獨特性及優越性。


    A series of thermal analyses with an effective thermal network method on heat transfer and flow friction characteristics of compact cold plates with discrete two-dimensional/three-dimensional electronic packages mounted on a multi-layer structure have been performed. Comparisons between the predicted thermal performance of discrete two-dimensional/three-dimensional electronic packages mounted on a multi-layer structure without or with compact cold plates by the present developed thermal analyzer and existing data have been made with satisfactory agreements. A series of parametric studies on thermal performance for discrete two-dimensional/three-dimensional electronic packages mounted on a multi-layer structure without and with compact cold plates have been explored, respectively.
    In addition, a systematical design optimization method with the Response Surface Methodology and Sequential Quadratic Programming techniques for performing the thermal optimization of compact cold plates with discrete two-dimensional/three-dimensional electronic packages mounted on a multi-layer structure under multiple constraints has been successfully developed. First, a statistical method for the sensitivity analysis has been performed to determine the critical factors of the design; and a response surface methodology has been applied to establish a series of performance correlations in terms of the design factors with a well-organized design of experiments. By employing the gradient-based numerical optimization technique, a series of globally optimal designs have been efficiently performed. With the developed design optimization method, two applications for thermal optimization of compact cold plates with discrete two-dimensional/three- dimensional electronic packages mounted on a multi-layer structure under multiple constraints have been systematically explored. They are (1) thermal optimal design for compact cold plates in CPU cooling and (2) thermal optimal design for compact cold plates in multi-layer PCB cooling.
    Furthermore, two novel interactive and user-friendly thermal optimal computer-aided design systems, which are composed of pre-processor, thermal network analyzer, optimizer, post-processor and user interface for automatically predicting the optimal thermal performance for generalized compact cold plates in CPU cooling and in multi-layer PCB cooling have been successfully developed. In the pre-processor, a user-friendly interface has been constructed to collect the required data for the thermal analyzer and optimizer. A thermal analyzer for compact cold plates with discrete two-dimensional/three-dimensional electronic packages mounted on a multi-layer structure has been successfully established by using an effective thermal network method. Corresponding to the presented design optimization method, the design optimizer has been established with the functions of conducting the design of experiments, automatically constructing response surface models, and then performing numerical optimization. After obtaining the optimal design, the real-time three-dimensional model, predicted color isotherms, and all the predicted performances have been displayed in the developed post-processor to provide a direct communication between user and computer. With the present developed thermal optimal computer-aided design systems, the optimal thermal design applied to generalized compact cold plates under multiple constraints with either a minimum thermal resistance or a minimum pressure drop/mass in CPU cooling and in multi-layer PCB cooling have been effectively performed. The superiority of the developed thermal optimal computer-aided design systems has been demonstrated.

    ABSTRACT i ACKNOWLEDGMENTS iv LIST OF TABLES xiii LIST OF FIGURES xvi NOMENCLATURE xlii CHAPTER 1 INTRODUCTION AND BACKGROUND 1 1.1 INTRODUCTION 1 1.2 LITERATURE SURVEY 3 1.2.1 Three-dimensional Multi-layer Structures with Discrete Heat Sources 3 1.2.2 Compact Cold Plates 15 1.2.3 Three-dimensional Multi-layer Structures Integrated with Compact Cold Plates 18 1.2.4 Design Optimization Techniques 20 1.2.5 Computer-Aided Design System 29 1.3 RESEARCH TOPICS AND OBJECTIVES 35 1.3.1 Thermal Analysis for Discrete Electronic Packages Mounted on a Multi-layer Structure 37 1.3.2 Thermal Analysis for Compact Cold Plates with Discrete Electronic Packages Mounted on a Multi-layer Structure 38 1.3.3 Thermal Optimal Design for Compact Cold Plates with Discrete Electronic Packages Mounted on a Multi-layer Structure 38 1.3.4 Development of Thermal Optimal CAD System for Compact Cold Plates in CPU Cooling 39 1.3.5 Development of Thermal Optimal CAD System for Compact Cold Plates in Multi-layer PCB Cooling 40 1.4 THESIS ORGANIZATION 41 CHAPTER 2 THERMAL ANALYSIS FOR DISCRETE ELECTRONIC PACKAGES MOUNTED ON A MULTI-LAYER STRUCTURE 44 2.1 ESTABLISHMENT OF THERMAL MODEL 44 2.1.1 Finite-Volume Model Generation 45 2.1.2 Thermal-Network Model Generation 49 2.2 THERMAL NETWORK ANALYZER 52 2.2.1 Fundamental Theory 53 2.2.2 Numerical Methods 61 2.2.3 Procedure of Performing Thermal Network Analysis 74 2.2.4 Grid Test 76 2.3 RESULTS AND DISCUSSION 78 2.3.1 Validation 78 2.3.2 Parametric Studies 88 CHAPTER 3 THERMAL ANALYSIS FOR COMPACT COLD PLATES WITH DISCRETE ELECTRONIC PACKAGES MOUNTED ON A MULTI-LAYER STRUCTURE 134 3.1 FUNDAMENTAL THEORIES FOR COMPACT COLD PLATES 134 3.1.1 Design Equation 135 3.1.2 Definition of LMTD and ε-Ntu Method 135 3.1.3 Fin and Weighted Passage Efficiency 137 3.1.4 Multi-Stack Cold Plate with Asymmetric Two-Sided Heating Loads 138 3.1.5 Generalized Prediction for Heat Transfer Surface Geometry 142 3.1.6 Pressure Drop and Mass Evaluations 144 3.1.7 Design Procedure for Multi-Stack Compact Cold Plates 145 3.2 THERMAL MODEL FOR COMPACT COLD PLATES WITH DISCRETE ELECRONIC PACKAGES MOUNTED ON A MULTI-LAYER STRUCTURE 147 3.3 THERMAL ANALYZER FOR COMPACT COLD PLATES WITH DISCRETE ELECRONIC PACKAGES MOUNTED ON A MULTI-LAYER STRUCTURE 148 3.4 RESULTS AND DISCUSSION 157 3.4.1 Validation 157 3.4.2 Parametric Studies 160 CHAPTER 4 THERMAL OPTIMAL DESIGN FOR COMPACT COLD PLATES WITH DISCRETE ELECTRONIC PACKAGES MOUNTED ON A MULTI-LAYER STRUCTURE 187 4.1 OPTIMAL DESIGN METHODOLOGY 187 4.1.1 Design of Experiments 187 4.1.2 Response Surface Methodology 188 4.1.3 Accuracy and Adequacy of Regression Model 196 4.1.4 Numerical Optimization Techniques 200 4.2 APPLICATIONS 203 4.2.1 Thermal Optimal Design for Compact Cold Plates in CPU Cooling 204 4.2.2 Thermal Optimal Design for Compact Cold Plates in Multi-layer PCB Cooling 226 CHAPTER 5 DEVELOPMENT OF THERMAL OPTIMAL CAD SYSTEM FOR COMPACT COLD PLATES IN CPU COOLING 303 5.1 CONFIGURATIONS OF THERMAL OPTIMAL CAD SYSTEM 303 5.2 PRE-PROCESSOR 304 5.2.1 Computer Graphics and User Interface 305 5.2.2 Problem Definition and Model Generating 306 5.2.3 Data Pre-processing 308 5.3 ANALYZER 309 5.4 OPTIMIZER 309 5.4.1 DOE Planning 309 5.4.2 Response Surface Regression 310 5.4.3 Numerical Optimization Programming 311 5.5 POST-PROCESSOR 312 5.5.1 Optimal Design Solutions 312 5.5.2 Realtime 3-D Modeling and Graphical Visualization 313 5.5.3 Data Post-processing and Report 314 5.6 INTEGRATION OF OPTIMAL CAD SYSTEM 314 5.7 APPLICATIONS 316 5.7.1 Optimal Thermal Design for Generalized Compact Cold Plates under Multiple Constraints with a Minimum Thermal Resistance 316 5.7.2 Optimal Thermal Design for Generalized Compact Cold Plates under Multiple Constraints with a Minimum Pressure Drop or Mass 324 CHAPTER 6 DEVELOPMENT OF THERMAL OPTIMAL CAD SYSTEM FOR COMPACT COLD PLATES IN MULTI-LAYER PCB COOLING 375 6.1 CONFIGURATIONS OF THERMAL OPTIMAL CAD SYSTEM 375 6.2 PRE-PROCESSOR 376 6.2.1 Problem Definition and Model Generating 377 6.2.2 Data Pre-processing 379 6.3 ANALYZER 379 6.4 OPTIMIZER 380 6.4.1 DOE Planning 380 6.4.2 Response Surface Regression 381 6.4.3 Numerical Optimization Programming 381 6.5 POST-PROCESSOR 382 6.5.1 Optimal Design Solutions 382 6.5.2 Realtime 3-D Modeling and Graphical Visualization 383 6.5.3 Data Post-processing and Report 384 6.6 INTEGRATION OF OPTIMAL CAD SYSTEM 384 6.7 APPLICATIONS 385 6.7.1 Optimal Thermal Design for Generalized Compact Cold Plates under Multiple Constraints with a Minimum Thermal Resistance 385 6.7.2 Optimal Thermal Design for Generalized Compact Cold Plates under Multiple Constraints with a Minimum Pressure Drop or Mass 394 CHAPTER 7 CONCLUSIONS AND RECOMMENDATIONS 456 7.1 CONCLUSIONS 456 7.2 RECOMMENDATIONS 460 REFERENCES 462 APPENDIX A COOLANT PROPERTIES 479 APPENDIX B MATERIAL PROPERTIES 482 VITA 488 LIST OF PUBLICATIONS 489

    [1] Kraus, A. D., and Bar-Cohen, A., 1983, Thermal Analysis and Control of Electronic Equipment, Hemisphere Publishing Corporation, Washington.
    [2] Lindsted, D. R., and Sturty, R., 1972, "Steady-State Junction Temperatures of Semiconductor Chips," In IEEE Trans. Electron Device, Vol.ED-19(1), pp.41-44.
    [3] Ellison, G. N., 1973, "The Effect of Some Composite Structures on the Thermal Resistance of Substrates and Integrated Circuit Chips," In IEEE Transactions on Parts, Hybrids, and Packaging, Vol.ED-20(3), pp.233-238.
    [4] Ellison, G. N., 1976, "The Thermal Design of an LSI Single-Chip Package," In IEEE Transactions on Parts, Hybrids, and Packaging, Vol.PHP-12(4), pp.371-378.
    [5] Ellison, G. N., 1984, Thermal Computations for Electronic Equipment, van Nostrand Reinhold Co., New York.
    [6] Palisoc, A. L., and Lee, C. C., 1988, "Thermal Properties of the Multilayer Infinite Plate Structure," J. Appl. Phys., 64, pp.410-415.
    [7] Palisoc, A. L., and Lee, C. C., 1988, "Exact Thermal Representation of Multilayer Rectangular Structure by Infinite Plate Structures Using the Method of Image," J. Appl. Phys., 64, pp.6851-6857.
    [8] Lee, C. C., and Palisoc A. L., 1988, "Real-Time Thermal Design of Integrated Circuit Devices," In IEEE Transactions on Components, Hybrids, and Manufacturing Technology, 11(4), pp.485-492.
    [9] Albers, J., 1994, "An Exact Solution of the Steady-State Surface Temperature for a General Multilayer Structure," Proceedings of the 10th IEEE, Semiconductor Thermal Measurement and Management Symposium, pp.129 -137.
    [10] Antonetti, V. W., and Yovanovich, M. M., 1984, “Thermal Contact Resistance in Microelectronic Equipment,” In Thermal Management Concepts in Microelectronic Packaging from Component to System, ISHM Technical Monograph Series 6984-003, pp.135-151.
    [11] Antonetti, V. W., Whittle, T. D., and Simons, R. E., 1993, “An Approximate Thermal Contact Conductance Correlation,” ASME Journal of Electronic Packaging, 115, pp.131-134.
    [12] Kuo, C. Y., Chen, H. T., Chen, P. L., and Hung, Y. H., 2004, “Real-Time Animated Thermal CAD System for 3-D Multilayer Structure Integrated with Compact Cold Plate,” the 9th Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, pp.685-692, Las Vegas, NV, USA, June 1-4.
    [13] Reill, M., 1994, "Iterative Direct Solution Method for Thermal Analysis of Electronic Equipment," Proceedings of the 44th IEEE, Electronic Components and Technology Conference, pp.644-652.
    [14] Petrosjanc, K. O., Kharitonov, I. A., Rybov, N. I. and Maltcev, P. P., 1995, "Software System for Semiconductor Devices, Monolith and Hybrid IC's Thermal Analysis," IEEE Design Automation Conference, pp.360-365.
    [15] Culham, J. R., and Yovanovich, M. M., 1997, “Thermal Characterization of Electronic Packages Using a Three-Dimensional Fourier Series Solution,” Advances in Electronic Packaging, EEP-Vol.19-2, pp.1955-1965, ASME, New York, USA, July 8-13.
    [16] Cooke, J. A., and Lee, S. W., 1989, “Finite Element Thermal Analysis of 144 Pin Plastic Flat Packs,” Proceedings of the 5th IEEE Semiconductor Thermal and Temperature Measurement Symposium, pp.59 - 62.
    [17] Aghazadeh, M. and Mallik, D., 1990, "Thermal Characteristics of Single and Multi-Layer High Performance PQFP Packages," Proceedings of the 6th IEEE, Semiconductor Thermal Measurement and Management Symposium, pp.33 -39.
    [18] Arbeitman, K. J., 1993, “Temperature Sensitivity to Node Spacing in ASTAP Finite Difference Modelling for Flat Cap Single- and Multi-chip Modules,” Proceedings of the 9th IEEE, Semiconductor Thermal Measurement and Management Symposium, pp.81- 87, Austin, TX, USA, February 2-4.
    [19] Weeks, W. T., Jimenez, A. J., Mahoney, G. W., Mehta, D., Qassemzadeh, H., and Scott, T. R., 1973, “Algorithms for ASTAP – A Network-Analysis Program,” In IEEE Transactions on Circuit Theory, Vol.CT-20(6), pp.628- 634.
    [20] Advanced Statistical Analysis Program (ASTAP) Reference Guide, Pub. No. LY20-0764, IBM Corporation, White Plains.
    [21] Lee, T. Y., 2000, "An Investigation of Thermal Enhancement on Flip Chip Plastic BGA Packages Using CFD Tool," In IEEE Transactions on Components and Packaging Technologies, Vol.ED-23(3), pp.481-489.
    [22] Pinjala, D., Khan, N., Xie L., Teo P. S., Wong, E. H., Iyer, M. K., Lee, C. and Rasiah, I. J., 2002, "Thermal Design of Heat Spreader and Analysis of Thermal Interface Materials (TIM) for Multi-Chip Package," Proceedings of the 52nd IEEE, Electronic Components and Technology Conference, pp.1119-1123.
    [23] Carmona, M., Eggers, G., Leseduarte, S., Legen, A., Wolter, A., Neugebauer, S. and Thomas, J., 2005, "Improved Methods for Memory Module Characterization," Proceedings of the 6th IEEE International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Micro-Electronics and Micro-Systems, pp.139-146.
    [24] Chen, P. L., Chang, S. F., Wu, T. Y., and Hung, Y. H., 2006, "A Thermal Network Approach for Predicting Thermal Characteristics of Three-Dimensional Electronic Packages," International Mechanical Engineering Congress and Exposition, Chicago, Illinois, USA, November 5-10.
    [25] Kraus, A. D., 1961, “Efficiency of the Cold Plate Heat Exchanger,” Proc. Natl. Aeronaut. Electron. Conf., Dayton, Ohio, USA, pp.381.
    [26] Kraus, A. D., 1962, “Optimization of the Cold Plate Heat Exchanger,” Proc. Natl. Aeronaut. Electron. Conf., Dayton, Ohio, USA, pp.78.
    [27] Kays, W. M., 1960, “Basic Heat Transfer and Flow Friction Characteristics of Six High Performance Heat Transfer Surfaces,” J. Eng. Power, 82, pp.27-32.
    [28] Kern, D. Q., and Kraus, A. D., 1972, Extended Surface Heat Transfer, McGraw-Hill Book Company, New York.
    [29] Pieper, R. J., and Kraus, A. D., 1995, "Cold Plate with Asymmetric Heat Loading Part I - The Single Stack," Advances in Electronic Packaging, EEP-Vol.10-2, ASME, New York, pp.865-870.
    [30] Pieper, R. J., and Kraus, A. D., 1995, "Cold Plate with Asymmetric Heat Loading Part I - The Double Stack," Advances in Electronic Packaging, EEP-Vol. 10-2, ASME, New York, pp.871-876.
    [31] Kays, W. M., and London, A. L., 1964/1984, Compact Heat Exchangers, 2nd/3rd ed., McGraw-Hill, New York.
    [32] LaHaye, P. G., Neugebauer, F. J., and Sakhuja, R. K., 1974, "A Generalized Prediction of Heat Transfer Surfaces," ASME J. Heat Transfer, 96, pp.511-517.
    [33] Kraus, A. D., 1985, User's Manual for Computer Packages (FINEFF, FINEVA, FLUIDFLO, MATRIX, CONDTUBE, PLATES, TUBES, CLDPLT, TASS, and TRAN), InterCept Software, CA, USA.
    [34] Fang, C. J., Wu, T. Y., Chen, P. L., Chang, S. F., and Hung, Y. H., 2005, "Thermal Computer-Aided Design for Compact Cold Plates," Journal of the Chinese Society of Mechanical Engineers, 26(1), pp.11-18.
    [35] Hung, Y. H., and Chun, Y. H., 1994, "Thermal Performance Analysis of Cold Plates for Multilayer Structures with Arbitrary Heating Loads," Heat Transfer in Electronic System, HTD-Vol.292, ASME, New York, pp.137-144.
    [36] Hung, Y. H., Chen, Y. Y., and Liu, C. Y., 1999, “Thermal CAD Package for Multilayer Printed Circuit Boards Integrated with Two-Stack Cold Plate,” Advances in Electronic Packaging 1999, EEP-Vol.26-2, pp.2177-2184.
    [37] Ye, Q. L., Liu, L. K., Liu, C. Y., and Hung, Y. H., 2002, “Multimedia Thermal CAD System for Electronics Multilayer Structure with Compact Cold Plate,” 8th Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, San Diego, USA, May 29-June 1.
    [38] Vanderplaats, G. N., 1993, Numerical Optimization Techniques for Engineering Design, McGraw-Hill, Singapore.
    [39] Wu, C. F., and Hamada, M., 2000, Experiments – Planning, Analysis, and Parameter Design Optimization, John Wiley & Sons, New York.
    [40] Belegundu, A. D., and Chandrupatla, T. R., 1999, Optimization Concepts and Applications in Engineering, Prentice Hall, New Jersey.
    [41] Lee, S., 1995, “Optimum Design and Selection of Heat Sinks,” 11th Annual IEEE Semiconductor Thermal Measurement and Management Symposium, San Jose, California, USA, Feb. 7-9, pp. 48-54.
    [42] Constans, E. W., Belegundu, A. D., and Kulkarni, A. K., 1994, “Optimization of a Pin-Fin Sink: A Design Tool,” International Mechanical Engineering Congress and Exposition, Chicago, Illinois, USA, Nov. 6-11, EEP-Vol.9, pp. 25-32.
    [43] Azer, K., and Mandrone, C. D., 1994, “Effect of Pin Fin Density of the Thermal Performance of Unshrouded Pin Fin Heat Sinks,” ASME J. Electronic Packaging, 116(4), pp. 306-309.
    [44] Shaukatullah, H., Storr, W. R., Hansen, B. J., and Gaynes, M. A., 1996, “Design and Optimization of Pin Fin Heat Sinks for Low Velocity Applications,” the 12th IEEE Semiconductor Thermal Measurement and Management Symposium, pp. 151-163.
    [45] Box, G. E. P., and Wilson, K. B., 1951, “On the Experimental Attainment of Optimum Conditions,” J. Royal Statistics Society, Series B(13), pp. 1-45.
    [46] Box, G. E. P., and Behnken, D. W., 1960, “Some New Three Level Designs for the Study of Quantitative Variables,” Technometrics, 2, pp.455-475.
    [47] Box, G. E. P., and Draper, N. R., 1987, Empirical Model-Building and Response Surfaces, John Wiley & Sons, New York.
    [48] Monthomery, D. C., 2001, Design and Analysis of Experiments, 5th Ed., John Wiley & Sons, New York.
    [49] Myers, G. N., and Montgomery, D. C., 2002, Response Surface Methodology, 2nd Ed,, John Wiley & Sons, New York.
    [50] Khuri, A. I., and Cornell, J. A., 1996, Response surfaces: designs and analyses, 2nd Ed., Marcel Dekker.
    [51] Fallon, M., Walton, A. J., Newsam, M. I., Axelradt, V., and Granikt, Y., 1995, “Integration of Costing, Yield and Performance Metrics into the TCAD Environment through the Combination of DOE and RSM,” IEEE International Symposium on Semiconductor Manufacturing, Austin, TX, USA, September 17-19, pp.266 - 270.
    [52] Cheng, H. C., Chen, W. H., and Chung, I. C., 2004, “Integration of Simulation and Response Surface Methods for Thermal Design of Multichip Modules,” In IEEE Transactions on Components and Packaging Technologies, 27(2), pp.359 - 372.
    [53] Dascalescu, L., Tilmatine, A., Aman, F., and Mihailescu, M. , 2004, “Optimization of Electrostatic Separation Processes Using Response Surface Modeling,” In IEEE Transactions on Industry Applications, 40(1), pp.53 - 59.
    [54] Cheng, Y., Xu, G., Zhu, D., Zhu, W., and Luo, L., 2006, “Thermal Analysis for Indirect Liquid Cooled Multichip Module Using Computational Fluid Dynamic Simulation and Response Surface Methodology,” In IEEE Transactions on Components and Packaging Technologies, 29(1), pp.39 - 46.
    [55] Rumelhart, D. E., Hinton, G. E., and Williams, R. J., 1986, “Learning Representation by Backpropagaion Error, ” Nature, 323 (9), pp. 533-536.
    [56] Chen, S., Billings, S. A., and Grant, P. M., 1990, “Non-linear System Identification Using Neural Network,” Int. J. Control, 1(6), pp. 1191-1214.
    [57] Ilonen, J., Kamarainen, J. K. and Lampinen, J., 2003, “Differential Evolution Training Algorithm for Feed-forward Neural Networks,” Neural Processing Letters, 17(1), pp.93-105.
    [58] Yoo, R. M., Lee, H., Chow K., Lee, H., and Lee, S., 2006, “Constructing a Non-Linear Model with Neural Networks for Workload Characterization,” IEEE International Symposium on Workload Characterization, San Jose, CA, USA, Oct., pp. 150-159.
    [59] Goldberg, D. E., 1989, Genetic Algorithms in Search, Optimization and Machine Learning, Addison-Wesley, Reading, MA.
    [60] Holland, J. H., 1992, “Genetic algorithms,” Sci. Am., pp. 44-50.
    [61] Krishnakumar, K., and Goldberg, D. E., 1992, “Control system optimization using geneic algorithms,” J. Guidance Control Synamics, 15(3), pp. 735-740.
    [62] Costa, M. C., Nabeta, S. I., Dietrich, A. B., Cardoso, J. R., Marechal, Y., and Coulomb, J. L., 2004, “Optimisation of a Switched Reluctance Motor Using Experimental Design Method and Diffuse Elements Response Rurface,” In IEEE Proceedings of Science, Measurement and Technology, 151, pp.411-413.
    [63] Idir, K., Chang, L., and Dai, H., 1998, “Improved neural network model for induction motor design,” IEEE Trans. Magn., 34(5), pp.2948–2951.
    [64] Dorica, M., and Giannacopoulos, D. D., 2006, “Response Surface Space Mapping for Electromagnetic Optimization,” In IEEE Transactions on Magnetics, Measurement and Technology, 42(4), pp.1123-1126.
    [65] Wu, A., Wu, K. Y., Chen, R. M. M., and Shen, Y., 1998, “Parallel Optimal Statistical Design Method with Response Surface Modelling Using Genetic Algorithms,” In IEEE Proceedings of Circuits, Devices and Systems, 145, pp.7-12.
    [66] Ilumoka, A. A., 1997, “Optimal transistor sizing for CMOS VLSI circuits using modular artificial neural networks,” in Proc. IEEE System Theory, West Hartford, CT.
    [67] Jolly, L., Jabbar, M. A., and Liu Q., 2005, “Design Optimization of Permanent Magnet Motors Using Response Surface Methodology and Genetic Algorithms,” In IEEE Transactions on Magnetics, Measurement and Technology, 41(10), pp.3928-3930.
    [68] Pan, S., Reilly, M. T., Di Fabrizio, E., Leonard, Q., Taylor, J. W., and Cerrina, F., 1994, “An Optimization Design Method for Chemically Amplified Resist Process Control,” In IEEE Transactions on Semiconductor Manufacturing, 7(3), pp.325-332.
    [69] Yoon, S. B., Jin, H., and Hyun, D. S., 1997, “A Method of Optimal Design of Single-Sided Linear Induction Motor for Transit,” In IEEE Transactions on Magnetics, Measurement and Technology, 33(5), pp.4215-4217.
    [70] Ravindran, S. S., 2002, “Optimal Control of Solid-Fuel Ignition Model using SQP Method,” In Proceedings of the 41st IEEE Conference on Decision and Control, 3, pp.3288-3293.
    [71] Kalyani, R. P., Crow, M. L., and Tauritz, D. R., 2006, “Optimal Placement and Control of Unified Power Flow Control devices using Evolutionary Computing and Sequential Quadratic Programming,” Power Systems Conference and Exposition, Atlanta, GA, USA, October 29 - November 1, pp.959 -964.
    [72] Han, S. Y., and Maeng, J. S., 2003, “Shape optimization of cut-off in a multi-blade fan/scroll system using neural network,” Int. J. Heat Mass Transfer, 46(5), pp.2833–2839.
    [73] Hadim, H., and Suwa, T., 2005, “A multidisciplinary design and optimization methodology for ball grid array packages using artificial neural networks,” ASME J. Electron. Packag., 127(3), pp.306-313.
    [74] Jambunathan, K., Hartle, S. L., Ashforth-Frost, S., and Fontama, V. N., 1996, “Evaluating convective heat transfer coefficients using neural networks,” Int. J. Heat Mass Transf., 39(11), pp.2329-2332.
    [75] Pacheco-Vega, A., Diaz, Sen, G., M., Yang, K.T. and McClain, R. L., 2001, “Heat Rate Predictions in humid Air-Water Heat Exchangers using correlations and neural networks,” ASME J. Heat Transfer, 123(2), pp.348-354.
    [76] Knight, R. W., and Gooding, J. S., “Optimal thermal design of forced convection heat sinks-analytical,” ASME J. Electron. Packag., 113, pp. 313-321, 1991.
    [77] Kraus, A. D., and Bar-Cohen, A., Design and Analysis of Heat Sinks, New York: John Wiley and Sons, Inc., 1995.
    [78] Zheng, N., and Wirtz, R. A., 2002, “Cylindrical Pin-Fin Fan-Sink Heat Transfer and Pressure Drop Correlations,” IEEE Transactions on Components and Packaging Technologies, Vol.ED-25(1), pp. 15-22.
    [79] Chen H. T., Horng, J. T., Chen, P. L., and Hung, Y. H., 2004, “Optimal Design for PPF Heat Sinks in Electronics Cooling Applications,” ASME Journal of Electronic Packaging, 126, pp.410-422.
    [80] Chen, H. T., Chen, P. L., Horng, J. T., and Hung, Y. H., 2005, “Design Optimization for Pin-Fin Heat Sinks,” ASME Journal of Electronic Packaging, 127(4), pp.397-406.
    [81] Wang, M. P., Chen, H. T., Horng, J. T., Wu, T. Y., Chen, P. L., and Hung, Y. H., 2005, “Thermal Optimal Design for Partially-Confined Compact Heat Sinks,” Proceedings of InterPACK’05, International Electronic Packaging Technical Conference and Exhibition, San Francisco, USA, July 17-22.
    [82] Wu, M. C., Peng, C. H., Lee, C. Y., Fang, C. J., and Hung, Y. H., 2005, “Optimal Design for Thermal Performance of a Heat Sink Integrated with Thermoelectric Cooler,” Proceedings of HT2005, 2005 ASME Summer Heat Transfer Conference, San Francisco, USA, July 17-22.
    [83] Horng, J. T., Chen, H. T., Chen, P. L., and Hung, Y. H., 2006, “Thermal Optimal Design for Parallel-Plain-Fin Heat Sinks by Using Neuro-Genetic Method,” Submitted to ASME Journal of Electronic Packaging, USA, March 10-12.
    [84] Chen, H. T., Chen, P. L., Horng, J. T., Chang, S. F., and Hung, Y. H., 2006, “Thermal Design Optimization for Strip-Fin Heat Sinks with a Ducted Air Flow,” Intersociety Conference on Thermal and Thermomechanical phenomena in Electronic Systems, San Diego, CA, USA, May 30-June 2.
    [85] Lee , C. Y., Wu, M. C., Peng, C. H., Fang, C. J., and Hung, Y. H., 2006, “Optimal Approach with Genetic Algorithm for Thermal Performance of Heat Sink/TEC Assembly,” Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, San Diego, CA, USA, May 30-June 2.
    [86] Chou, C. L., 1999, “Multimedia Computer-Aided Design System for Thermal Control of Notebook Computers,” Master’s Thesis, Department of Power Mechanical Engineering, National Tsing Hua University, Taiwan, R.O.C..
    [87] Lin, H. C., Liu, L. K., and Hung, Y. H., 2001, "Thermal Computer-Aided Design for Switching Power Supplies," International Electronic Packaging Technical Conference and Exhibition, Kauai, Hawaii, USA, July 8-13.
    [88] Chen, P. L., Chang, S. F., and Hung, Y. H., 2006, “Thermal Computer-Aided Design of Heat Sinks for CPU Cooling Applications,” the 17th International Symposium on Transport Phenomena, Japan, September 4-8.
    [89] Hung, Y. H., and Chiou, Y. M., 1996, "Computer-Aided Design for Multi-Layer Cold Plates with Arbitrary Heating Loads," International Electronics Packaging Society Conference, Austin, TX, USA, September 29-October 1, pp. 285–296.
    [90] Wang, L. S., Liu, C. Y. and Hung, Y. H., 1998, "Thermal Computer-Aided Design for Multi-Layer Structures Integrated with Compact Cold Plate," the 11th International Symposium on Transport Phenomena, Hsichu, Taiwan, Nov.29-Dec.3, pp.17-22
    [91] Pierce, B. L., and Stumpf, H. J., 1969, “TAP-A – A Program for Computing Transient or Steady-State Temperature Distribution,” Westinghouse Astronulear Laboratory, USA.
    [92] Antonetti, V. W., Whittle, T. D., and Simons, R. E., 1991, “An Approximate Thermal Contact Conductance Correlation,” In Experimental/ Numerical Heat Transfer in Combustion and Phase Change, HTD-Vol.170, ASME, New York, pp.131-134.
    [93] Ling, F. F., 1958, “On Asperity Distributions of Metallic Surfaces,” Journal of Applied Physics, 29(8).
    [94] Mikic, B. B., and Rohsenow, W. M., 1966, “The Effect of Surface Roughness and Waviness upon the Overall Thermal Contact Resistance,” EPL Rept. No. 79361-43, Massachusetts Institute of Technology, Cambridge, Mass..
    [95] Yovanovich, M. M., 1981, “New Contact and Gap Correlations for Conforming Rough Surfaces,” AlAA 16th Thermophysics Conference, Palo Alto, CA, USA.
    [96] Song, S., and Yovanovich, M. M., 1987, “Correlation of Thermal Accommodation Coefficient for Engineering Surfaces”, In Fundamentals of Conduction and Recent Developments in Contact Resistance, HTD-Vol.69, ASME, New York, pp.107-116.
    [97] Xie M. and Toh K. C., 2002, “An Adaptable Compact Thermal Model for BGA Packages,” IEEE Electronic Packaging Technology Conference, pp.304-311.
    [98] EIA/JESD 51-2 Integrated Circuit Thermal Test Method Environment Conditions – Natural Convection.
    [99] Loh C. V., Toh K. C., Pinjala D. and Iyer M. K., 2000, “Development of Effective Compact Models for Depopulated Ball Grid Array Packages,” 3rd Electronic Packaging Technology Conference, Singapore.
    [100] Shullhan, R., Fredholm, M., Monahan, T., Agarwall, A., and Kozarek B., 1991, “Thermal Modeling and Analysis of Pin Grid Arrays and Multichip Modules,” Proceedings of the 7th IEEE Semiconductor Thermal Measurement and Management Symposium, Phoenix, AZ, USA, pp.110-116
    [101] Rosten, H.I., Parry, J.D., Addison, J.S., Viswanath, R., Davies, M., Fitzgerald, E., 1995, “Development, validation and application of a thermal model of a plastic quad flat pack,” Proceedings of the 45th Electronic Components and Technology Conference, pp.1140-1151.
    [102] Eveloy, V., Rodgers, P., Lohan, J., 2002, “Comparison of numerical predictions and experimental measurements for the transient thermal behavior of a board-mounted electronic component,” Proceedings of the 8th Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, pp.36-45.
    [103] Kraus, A. D., 1997, “Developments in the Analysis of Finned Arrays,” ASME 32nd National Heat Transfer Conference, Baltimore, Maryland, August 10-12.
    [104] Liu, C. Y., and Hung, Y. H., 2003, “Heat Transfer and Flow Friction Characteristics for Compact Cold Plates,” ASME J. Electronic Packaging, 125, pp.104-113.

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