本論文詳細的探討了各種新穎奈米尺度無接面鰭式場效電晶體的元件製作方法，電特性，可靠度分析，以及其在三維堆疊積體電路中應用的可能性。本文主要共分成三大方向，第一部分是探討我們成功製作出的通道厚度僅2奈米的無接面電晶體特性及其可靠度分析，我們採用氧化薄化的方法來形成極薄膜通道將能得到非常好的電晶體特性，由於薄化可使通道多晶晶粒大小的減小以及缺陷的降低，可得到近似單晶的通道，電性上也展現出非常低的漏電流以及近乎於理想的陡峭臨界曲線，開關電流比可達到十的八次方，此研究已被2013年的VLSI Technology所接受，無接面電晶體可為未來低靜態功率消耗之元件。值得一提的是我們以多晶矽做出來的元件，在Vth隨溫度的飄動上，與單晶的元件行為類似。另外，本研究亦發現其崩潰電壓達到五十伏，遠高於類似尺寸的傳統型薄膜電晶體以及在高壓應用下常用的橫向擴散金氧半場效應電晶體，而這主要歸功於無接面電晶體的結構本質像一個電阻，使得電場可以均勻的分佈在整個半導體區域內，而非一般的傳統型電晶體只集中在通道汲極的接面之上。因此無接面電晶體對於高壓元件的應用也是具有潛力的。
雖然無接面薄膜電晶體為一種未來可行的元件，因其製程簡單、熱預算少、短通道效應不明顯等優點。但由於無接面式電晶體需做成薄膜型態才能將通道關上，此原因使得無接面式薄膜電晶體的飽和電流受到壓制，呈現小電流的情況。因此，此篇論文第二部分提出升抬式汲源極結合無接面式薄膜電晶體，藉此降低串聯電阻，使得飽和電流升高。在基本電性上，汲源極抬升使得無接面薄膜晶體的飽和電流能達到1μA 比起之前文獻高出快十倍。使用抬升式汲源極結構可保留原本無接面電晶體薄通道的特性，其基本電性如SS將近100mV/dec.;漏電流低至10-14A，因此使用升抬式汲源極可整合博通到結構，進而使得元件特性提升。在可靠度分析中，我們將有升抬式汲源極的無接面電晶體施予加熱分析，從基本電性圖中，看出重要參數的變化如:SS，Vth，Ion ，Ioff ，藉此分析元件的熱穩定性，以及與溫度的相依性。對於stress的實驗中，在匝極施予固定的偏壓，看元件在連續偏壓下裂化的程度。比較P型與N型元件，可發現在此種stress條件下，N型元件相較於P型元件抗stress. 在升抬式汲源極無接面電晶體中，我們應用了雙匝極(Dual Gate)的概念，在同一層中，我們同時定義出兩條匝極，控制同一條通道，此種元件在操作時發現藉由兩條匝極施予不同的電壓條件，元件的Vth可做彈性的調變，對於邏輯元件而言，這是一個很好的應用。在此部分的研究中，討論了操作電壓與元件電性的變化。
在第三部分的研究中，成功做出一種新穎的無接面電晶體。由於無接面電晶體需要做薄才能運作，但薄化的製程不易控制，因此本篇提出利用”bulk”元件的概念，做出混合式反參雜通道(Hybrid P/N channel)的薄膜電晶體，藉著不同參雜，產生空乏區，使等效通道變薄。基本的結構圖、電性圖與模擬圖將會在內文中提及與討論，此研究已發表於2014年的IEDM頂尖會議。在混合式反參雜通道的薄膜電晶體中，除了使用不同的摻雜濃度調變臨界電壓，接著更進一步，使用背向閘極(back-gate)可以在不改變製程的情況下達到多重臨界電壓的調變，除可節省製程預算，也能讓元件特性更佳化，例如同時可以增加開電流與同時降低漏電流，使用背向閘極偏壓的方式，已成為低功率電路(low-power circuit)和功率性能管理中的關鍵技術，可獲得所期望的臨界電壓調變。我們亦成功將混合式反參雜通道的薄膜電晶體做多層PNPN堆疊元件結構，能應用於堆疊3D積體電路中，來提高電晶體密度以延續Moore’s law，並可應用於次世代高畫質的主動式平面顯示器與其面板和高密度記憶體所使用，極具學術與產業界應用價值，是一重大且具影響力之研究課題。此3D堆疊的電晶體結構為多層元件的製作方式，來增加電子元件的密度，並預期使P/N結構的開電流隨著元件層數而增加，但仍可維持一樣好的電特性，可以使開電流增加並同時讓關電流下降(Ion-Ioff)，很低次臨界擺幅(SS)和良好的短通道效應控制力(DIBL)特性，此研究已被2016年的VLSI Technology所接受。

In this work, we comprehensively study the device fabrication, electrical characteristic, and reliability of the various novel nano-scale Junctionless fin field-effect transistors for three-dimensional (3D) stacked IC application. In the first part of this work, the LTPS JL-GAA TFTs with ultra-thin channel are successfully fabricated by oxidation thinning method. Our JL device shows quasi-crystal channel due to the reduction of grain boundaries and defects, beneficial for excellent electrical performance. This process is simple and compatible with existing CMOS processes. Such a GAA JL feature simplifies the S/D engineering and the DIBL is very small. The low Ioff and steep SS in JL-GAA TFTs result in high on/off current ratio up to 108, which can be used in high-speed and low power consumption applications. We also measure the breakdown voltage of such device and compare it to IM TFT. Our JL TFT obtains higher breakdown voltage because the electric field in the device is uniformly distributed liked a resistor, indicating the potential of high-voltage application.
The junctionless transistor is proposed to be a future device because of the simple fabrication and suffered the suppression of On-current owing to the thin channel structure. In the second part of this work, the raised source and drain (RSD) structure is combined with the juncitonless transistor for the improvement of On-current. In the basic electrical measurement, the On-current of the RSD device almost reaches 1A that is ten times for that of the non-RSD devices. The RSD juncitonless device gets the steep sub-threshold swing (SS=100mV/dec.) and the Off-current is low (10-14A) due to the remained thin channel structure. For reliability experiment, the temperature and the stress tests are taken for the RSD junctionless device. When the RSD junctionless device is heated up, the positive shifting of threshold voltage, degradation of SS and increase of the On-current as well as Off-current could be observed. The stress operation makes the electrical characteristics of the RSD junctionless device changes due to the trapped carriers injected by gate at the edges of the gate insulator. The special structure of the N-type RSD junctionless device called the dual gate is discussed. The two gates at the same layer would make the threshold voltage become tunable flexibly. For the N-type RSD junctionless device, when the bias-gate voltage is negative, the Vth would shift toward the right side. When the bias gate voltage is positive, the Vth would shift toward the left side. It should be noticed that the shifts of Vth is linear regression with the bias gate voltage as well as the change of the On-current fits the quadratic regression.
In the last part of this work, the new structure of the junctionless device is brought up called Hybrid P/N channel. The idea of the Hybrid P/N channel is intrigued by the bulk device. The different type layers are stacked as the channel to enhance the simplicity of the fabrication for the thin channel. The performance of the Hybrid P/N is good with the low SS (64mV/dec.). The simulation is added for proving the existence of the depletion region. Using different doping concentration in Hybrid P/N channel devices can adjust Vth. In further, using back-gate achieves device multi-Vth adjustment without adding process budget and device performance optimization for increased Ion simultaneously decreased Ioff via negative back-gate bias, which becomes the key technology in low-power circuit and power management applications. We also success demonstrates a 3D stacked hybrid P/N layer in 3D stacked integrated circuit (IC) applications to increase transistor density for continuing Moore’s law, which provide valuable information regarding their practical industrial and academic applications. The 3D stacked hybrid P/N layer can increase on-state current and maintain low leakage current, small SS and great DIBL characteristics of short channel effect.

Chapter 1
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Chapter 2
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[2-21] R. D. Trevisoli , R. T. Doria , M. de Souza and M. A. Pavanello, "Threshold voltage in junctionless nanowire transistors," Semicond. Sci. Technol., vol. 26, no. 10, pp. 105009, 2011.
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[2-23] H. B. Chen, Y. C. Wu, C. Y. Chang, M. H. Han, N. H. Lu, Y. C Cheng, in VLSI Symp. Tech. Dig. 2013, pp. 232-233.

Chapter 3
[3-1] C. W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, and J. P. Colinge, “Junctionless multigate field-effect transistor,” Appl. Phys. Lett., vol. 94, no. 5, pp. 053511, Feb. 2009.
[3-2] J. P. Colinge, C. W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O’Neill, A. Blake, M. White, A. M. Kelleher, B. McCarthy, and R. Murphy, “Nanowire transistors without junctions,” Nat. Nanotechnol., vol. 5, no. 3, pp. 225-229, Mar. 2010.
[3-3] J. P. Colinge, C. W. Lee, I. Ferain, A. Afzalian, N. D. Akhavan, R. Yan, P. Razavi, R. Yu, A. N. Nazarov, R.T. Doria, “Reduced electric field in junctionless transistors,” Appl. Phys. Lett., vol. 96, pp. 073510, Feb. 2010.
[3-4] R. Rios, A. Cappellani, M. Armstrong, A. Budrevich, H. Gomez, R. Pai, N. Rahhal-orabi and K. Kuhn, ”Comparison of Junctionless and Conventional Trigate Transistors With Lg Down to 26 nm”, IEEE Electron Device Lett., vol.32, no.9, pp. 1170-1172, Sept. 2011.
[3-5] H. C. Lin, C. I. Lin, T. Y. Huang, “Characteristics of n-Type Junctionless Poly-Si Thin-Film Transistors with an Ultrathin Channel,” IEEE Electron Device Lett., vol. 33, no.1, pp. 53-55, Jan. 2012.
[3-6] C. J. Su, T. I. Tsai, Y. L. Liou, Z. M. Lin, H. C. Lin, and T. S. Chao, "Gate-All-Around Junctionless Transistors With Heavily Doped Polysilicon Nanowire Channels," IEEE Electron Device Lett., vol. 32, no.4, pp. 521-523, Apr. 2011.
[3-7] H. B. Chen, C. Y. Chang, N. H Lu, J. J. Wu, M.H. Han, Y.C. Cheng, and Y.C. Wu, "Characteristics of Gate-All-Around Junctionless Poly-Si TFTs With an Ultrathin Channel," IEEE Electron Device Lett., vol. 34, no.7, pp. 897-899, Jul. 2010.
[3-8] S. J. Choi, J. W. Han, S. Kim, D. I. Moon, M. Jang, and Y. K. Choi, “A novel TFT with a laterally engineered bandgap for of 3D logic and flash memory,” in VLSI Symp. Tech. Dig., 2010, pp. 111-112.
[3-9] H. C. Lin, C. I. Lin, Z. M. Lin, B.S. Shie, and T. Y. Huang, “Characteristics of Planar Junctionless Poly-Si Thin-Film Transistors With Various Channel Thickness,” IEEE Trans. Electron Devices, vol. 60, no. 3, pp. 1142-1148, Mar. 2010.
[3-10] V. Kursun. and E.G. Friedman, Multi-Voltage CMOS Circuit Design. New York, Wiley, 2007.
[3-11] S. Barraud, R. Coquand, M. Casse, M. Koyama, J.-M. Hartmann, V. Maffini-Alvaro, C. Comboroure, C. Vizioz, F. Aussenac, O. Faynot and T.Poiroux, ”Performance of omega-shaped-gate silicon nanowire MOSFET with diameter down to 8 nm,” IEEE Electron Device Lett., vol. 33, no. 11, pp. 1526-1528, 2012.
[3-12] R. D. Trevisoli , R. T. Doria , M. de Souza and M. A. Pavanello, "Threshold voltage in junctionless nanowire transistors," Semicond. Sci. Technol., vol. 26, no. 10, pp. 105009, 2011.
[3-13] C. W. Lee, A. Borne, I. Ferain, A. Afzalian, R. Yan, N. D. Akhavan, P. Razavi, J. P. Colinge, “High-Temperature Performance of Silicon Junctionless MOSFETs,” IEEE Transactions on Electron Devices, vol. 57, no. 3, pp. 620-624, Nov. 2010.
[3-14] TCAD Sentaurus Device, Ver. E-2010.12, Synopsys, Inc., Mountain View, CA, USA, Mar. 2011.
[3-15] A. Walker, F. W. Jeffrey, A. Gilbert, H. Karin, User’s Manual for Synopsys Sentaurus Device. Ottawa, ON, Canada, 2010.
[3-16] M. G. Ancona, and G. J. Iafrate, “Quantum correction to the equation of state of an electron gas in a semiconductor,” Phys. Rev. B vol. 39, no. 13, pp. 9536-9540, 1989.
[3-17] S. Reggiani, M. Valdinoci, L. Colalongo, M. Rudan, G. Baccarani, A. D. Stricker, F. Illien, N. Felber, W. Fichtner and L. Zullino, ”Electron and hole mobility in silicon at large operating temperatures.Part 1: Bulk mobility,” IEEE Transactions on Electron Devices, vol. 49, no. 3, pp. 490-499, Mar. 2002.

Chapter 4
[4-1] M. H. Han, C. Y. Chang, H. B. Chen, J. J. Wu, Y. C. Cheng, and Y. C. Wu, "Performance comparison between bulk and SOI junctionless transistors," IEEE Electron Device Lett., vol. 34, no. 2, pp. 169-171, Feb. 2013.
[4-2] J. P. Colinge, C.-W. Lee, I. Ferain, N. D. Akhavan, R. Yan, R. Razavi, R. Yu, A. N. Nazarov, and R. T. Doria, "Reduced electric field in junctionless transistors," Appl. Phys. Lett., vol. 96, no. 7, pp. 073510-1-073510-3, Feb. 2010.
[4-3] J. P. Colinge, C. W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O'Neill, A. Blake, M. White, A. M. Kelleher, B. McCarthy, and R. Murphy, "Nanowire transistors without junctions, " Nat. Nanotechnol., vol. 5, no. 3, pp. 225-229, Mar. 2010.
[4-4] S. Barraud, M. Berthom?, R. Coquand, M. Cass?, T. Ernst, M.-P. Samson, P. Perreau, K. K. Bourdelle, O. Faynot, and T. Poiroux, "Scaling of Trigate Junctionless Nanowire MOSFET with Gate Length down to 13 nm, "IEEE Electron Device Lett., vol. 33, no.9, pp. 1225-1227, Sept. 2012.
[4-5] H. C. Lin, C. I. Lin, T. Y. Huang, "Characteristics of n-type junctionless poly-Si thin-film transistors with an ultrathin channel," IEEE Electron Device Lett., vol. 33, no.1, pp. 53-55, Jan. 2012.
[4-6] C. J. Su, T. I. Tsai, Y. L. Liou, Z. M. Lin, H. C. Lin, and T. S. Chao, "Gate-All-Around junctionless transistors with heavily doped polysilicon nanowire channels," IEEE Electron Device Lett., vol. 32, no.4, pp. 521-523, Apr. 2011.
[4-7] H. B. Chen, Y. C. Wu, C. Y. Chang, M. H. Han, N. H. Lu, and Y. C. Cheng, "Performance of GAA poly-Si Nanosheet (2nm) channel of Junctionless Transistors with ideal Subthreshold Slope," in Proc. VLSI Symp. Tech. Dig., pp. 232, 2013.
[4-8] S. J. Choi, J. W. Han, S. Kim, D. I. Moon, M. Jang, and Y. K. Choi, "A novel TFT with a laterally engineered bandgap for of 3D logic and flash memory," in VLSI Symp. Tech. Dig., 2010, pp. 111-112.
[4-9] L. W. Chu, P. T. Liu, and M. D. Ker, "Design of Integrated Gate Driver With Threshold Voltage Drop Cancellation in Amorphous Silicon Technology for TFT-LCD Application," IEEE J. Display Technol., vol. 7, no.12, pp. 657-664, Dec. 2011.
[4-10] TCAD Sentaurus Device, Ver. E-2010.12, Synopsys, Inc., Mountain View, CA, USA, Mar. 2011.
[4-11] V. Kursun and E. G. Friedman: Multi-Voltage CMOS Circuit Design. New York, NY, USA: John Wiley, 2006.
[4-12] D. K. Schroder: Semiconductor Material and Device Characterization. New York, NY, USA: Wiley, 2006.
[4-13] C. W. Lee, A. Borne, I. Ferain, A. Afzalian, R. Yan, N. Dehdashti, and J. P. Colinge, “High-Temperature Performance of Silicon Junctionless MOSFETs,” IEEE Transactions on Electron Devices, vol. 57, pp. 620-625, 2010.
[4-14] S. S. Chung et al., “AHE: A new low voltage/high speed programming scheme for both n- and p-channel flash EEPROM’s,” Extended Abs. SSDM, pp. 612-613, 2002.

Chapter 5
[5-1] Q. Liu et al., “Impact of back bias on ultra-thin body and BOX (UTBB) devices,” in Symp. VLSI Technol. Tech. Dig., Jun. 2011, pp. 160-161.
[5-2] K. Ota, M. Saitoh, C. Tanaka, and T. Numata, “Threshold voltage control by substrate bias in 10-nm-Diameter Tri-Gate Nanowire MOSFET on Ultrathin BOX,” IEEE Electron Device Lett., vol. 34, no. 2, pp. 187-189, Feb. 2013.
[5-3] Ti Skotnicky, “Competitive SoC with UTBB SOI,” in Proc. IEEE SOI Conf., Tempe, AZ, Oct.3–6, 2011, pp.1-61.
[5-4] J. P. Colinge, C. W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O’Neill, A. Blake, M. White, A. M. Kelleher, B. McCarthy, and R. Murphy, “Nanowire transistors without junctions, ”Nat. Nanotechnol., vol. 5, no. 3, pp. 225-229, Mar. 2010.
[5-5] R. Rios, A. Cappellani, M. Armstrong, A. Budrevich, H. Gomez, R. Pai, N. Rahhal-orabi, and K. Kuhn, “Comparison of junctionless and conventional trigate transistors with Lg down to 26 nm,” IEEE Electron Device Lett., vol. 32, no. 9, pp. 1170-1172, Sep. 2011.
[5-6] S. J. Choi, J. W. Han, S. Kim, D. I. Moon, M. Jang, and Y. K. Choi, “A novel TFT with a laterally engineered bandgap for of 3D logic and flash memory,” in Symp. VLSI Tech. Dig, Jun. 2010, pp. 111-112.
[5-7] H. B. Chen, Y. C. Wu, C. Y. Chang, M. H. Han, N. H. Lu, and Y. C. Cheng, “Performance of GAA poly-Si nanosheet (2 nm) channel of junctionless transistors with ideal subthreshold slope,” in Symp. VLSI Technol. Tech. Dig., Jun. 2013, pp. 232-233.
[5-8] P. Singh, N. Singh, J. Miao, W.-T. Park, and D.-L. Kwong, “Gate-all-around junctionless nanowire MOSFET with improved low-frequency noise behavior,” IEEE Electron Device Lett., vol. 32, no. 12, pp. 1752-1754, Dec. 2011.
[5-9] C. J. Su et al., “Gate-All-Around junctionless transistors with heavily doped polysilicon nanowire channels,” IEEE Electron Device Lett., vol. 32, no. 4, pp. 521-523, Apr. 2011.
[5-10] Y. C. Cheng, H. B. Chen, C. S. Shao, J. J. Su, Y. C. Wu, C. Y. Chang and T. C. Chang, “Performance enhancement of a novel P-type junctionless transistor using a hybrid poly-Si fin channel,” in IEDM Tech. Dig., Dec. 15-17, 2014, pp. 622–625.
[5-11] S. M. Lee and J. T. Park, “The impact of substrate bias on the steep subthreshold slope in junctionless MuGFETs ,” IEEE Transactions on Electron Devices, vol. 60, no. 11, pp. 3856-3861, Nov. 2013.
[5-12] TCAD Sentaurus Device, Ver. J-2014.09, Synopsys, Inc., Mountain View, CA, USA.
[5-13] L.-W. Chu, P.-T. Liu, and M.-D. Ker, “Design of integrated gate driver with threshold voltage drop cancellation in amorphous silicon technology for TFT-LCD application,” J. Display Technol., vol. 7, no. 12, pp. 657-664, Dec. 2011.
[5-14] A. J. Walker, S. B. Herner, T. Kumar, and E.-H. Chen, “On the conduction mechanism in polycrystalline silicon thin-film transistors,” IEEE Trans. Electron Devices, vol. 51, no. 11, pp. 1856-1866, Nov. 2004.
[5-15] T. I. Tsai, K. M. Chen, H. C. Lin, T. Y. Lin, C. J. Su, T.S. Chao, and T.Y. Huang, “Low-operating-voltage ultrathin junctionless poly-Si thin-film transistor technology for RF applications,” IEEE Electron Device Lett., vol. 33, no. 11, pp. 1565-1567, 2012.

Chapter 6
[6-1] E. K. Lai, H. T. Lue, Y. H. Hsiao, J. Y. Hsieh, C. P. Lu, S. Y. Wang, L. W. Yang, T. Yang, K. C. Chen, J. Gong, K. Y. Hsieh, R. Liu, and C. Y. Lu, “A multi-layer stackable thin-film transistor (TFT) NAND-type Flash memory,” in IEDM Tech. Dig., 2006, pp. 1-4.
[6-2] C. H. Hung, H. T. Lue, K. P. Chang, C. P. Chen, Y. H. Hsiao, S. H. Chen, Y. H. Shih, K. Y. Hsieh, M. Yang, J. Lee, S. Y. Wang, T. Yang, K. C. Chen, and C. Y. Lu, “A Highly Scalable Vertical Gate (VG) 3D NAND Flash with Robust Program Disturb Immunity Using a Novel PN Diode Decoding Structure,” in Symp. VLSI Technol. Tech. Dig., Jun. 2011, pp. 68–-69.
[6-3] H.T. Lue, T.H. Hsu, Y.H. Hsiao, S. P. Hong, M. T. Wu, F. H. Hsu, N. Z. Lien, S.Y. Wang, J.Y. Hsieh, L.W. Yang, T. Yang, K.C. Chen, K.Y. Hsieh, and C.Y. Lu, "A Highly Scalable 8-Layer 3D Vertical-Gate (VG) TFT NAND Flash Using Junction-Free Buried Channel BE-SONOS Device," in Symp. VLSI Technol. Tech. Dig., Jun. 2010, pp. 131-132.
[6-4] J. Jang, H.S. Kim, W. Cho, H. Cho, J. Kim, S. I. Shim, Y. Jang, J.H. Jeong, B.K. Son, D. W. Kim, K. Kim, J. Shim, J. S. Lim, K.H. Kim, S. Y. Yi, J.Y.Lim, D. Chung, H.C. Moon, S. Hwang, J.W. Lee, Y.H. Son, U.I. Chung and W.S. Lee, "Vertical Cell Array using TCAT(Terabit Cell Array Transistor) Technology for Ultra High Density NAND Flash Memory," in Symp. VLSI Technol. Tech. Dig., Jun. 2009, pp. 192-193.
[6-5] J. P. Colinge, C.-W. Lee, I. Ferain, N. D. Akhavan, R. Yan, R. Razavi, R. Yu, A. N. Nazarov, and R. T. Doria, “Reduced electric field in junctionless transistors,” Appl. Phys. Lett., vol. 96, no. 7, pp. 073510-1-073510-3, Feb. 2010.
[6-6] J. P. Colinge, C. W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O’Neill, A. Blake, M. White, A. M. Kelleher, B. McCarthy, and R. Murphy, “Nanowire transistors without junctions, ” Nat. Nanotechnol., vol. 5, no. 3, pp. 225-229, Mar. 2010.
[6-7] S. Barraud, M. Berthomé, R. Coquand, M. Cassé, T. Ernst, M.-P. Samson, P. Perreau, K. K. Bourdelle, O. Faynot, and T. Poiroux, “Scaling of Trigate Junctionless Nanowire MOSFET with Gate Length down to 13 nm, ” IEEE Electron Device Lett., vol. 33, no.9, pp. 1225-1227, Sept. 2012.
[6-8] H. C. Lin, C. I. Lin, T. Y. Huang, “Characteristics of n-type junctionless poly-Si thin-film transistors with an ultrathin channel,” IEEE Electron Device Lett., vol. 33, no.1, pp. 53-55, Jan. 2012.
[6-9] H. B. Chen, Y. C. Wu, C. Y. Chang, M. H. Han, N. H. Lu, and Y. C. Cheng, “Performance of GAA poly-Si Nanosheet (2nm) channel of Junctionless Transistors with ideal Subthreshold Slope,” in Proc. VLSI Symp. Tech. Dig., pp. 232, 2013.
[6-10] TCAD Sentaurus Device, Ver. J-2014.09, Synopsys, Inc., Mountain View, CA, USA.
[6-11] Y. C. Cheng, H. B. Chen, C. S. Shao, J. J. Su, Y. C. Wu, C. Y. Chang, T. C. Chang, “Performance Enhancement of a Novel P-type Junctionless Transistor Using a Hybrid Poly-Si Fin Channel,” in IEDM Tech. Dig., 2014, pp. 622-625.
[6-12] J. K. Park, S. Y. Kim, K. H. Lee, S. H. Pyi, S. H. Lee, and B. J. Cho, “Surface-controlled Ultrathin (2 nm) Poly-Si Channel Junctionless FET owards 3D NAND Flash Memory Applications,” in Proc. VLSI Symp. Tech. Dig., pp. 98-99, 2014.
[6-13] Y. J. Lee, T. C. Cho, K. H. Kao, P. J. Sung, F. K. Hsueh, P. C. Huang, C. T. Wu, S. H. Hsu, W. H. Huang, H. C. Chen, Y. Li, M. I. Current, B. Hengstebeck, J. Marino, T. Büyüklimanli, J. M. Shieh, T. S. Chao, W. F. Wu, and W. K. Yeh, “A Novel Junctionless FinFET Structure with Sub-5nm Shell Doping Profile by Molecular Monolayer Doping and Microwave Annealing,” in IEDM Tech. Dig., 2014, pp. 788-791.
[6-14] M. S. Yeh, Y. C. Wu, M. H. Wu, Y. R. Jhan, M. H. Chung, and M. F. Hung, “High Performance Ultra-Thin Body (2.4nm) Poly-Si Junctionless Thin Film Transistors with a Trench Structure,” in IEDM Tech. Dig., 2014, pp. 618-621.
[6-15] P. Y. Kuo, J. Y. Lin, and T. S. Chao, “Implantation Free GAA Double Spacer Poly-Si Nanowires Channel Junctionnless FETs with Sub-1V Gate Operation and Near Idea Subthreshold Swing,” in IEDM Tech. Dig., 2015, pp. 133-136.