無線通訊系統以工作的頻率可以分成三個主要系統方塊，分別是射頻(RF)，中頻(IF)，以及基頻(Base band)。基頻和中頻的部分由於工作頻率較低，電路中又不須要有電感而且可以用數位的方式來製作，所以很適合以CMOS製程來實現，而RF的部分為了要阻抗匹配以及設計上的需要，所以須要將面積大而又損耗的電感導入使用，也因此使得RF IC電路的設計考量比基頻和中頻更加地複雜，並且需要更精確的模擬Spice Model，使得製作出來的晶片精確度提升。
射頻、中頻和基頻整合在同一顆晶片上，不但低功率省電，IC面積小，單電壓易整合，而且使得目前市面上所有電腦以及通訊相關領域的產品有重大的影響。最明顯的例子就是手機、PDA和Notebook將可以愈作體積愈小，愈來愈省電使得待機時間增長，重量愈來愈輕使得可攜性增高，並且適用於大量製造生產，加速產品的普及和生產成本的降低，所以CMOS RF的IC製作成為目前相當熱門的研究發展主題。

CMOS RFIC的快速發展使得射頻、中頻和基頻整合System on Chip (SOC)的製作可行，因此可大量的降低成本，並加速量產。在本論文中，以台灣積體電路公司0.35微米CMOS製程來製作以一操作頻率在1.95GHz之間，可調整增益的低雜訊放大器以及吉爾伯特混波器於一晶片上(1.5微米乘以1.5微米大小的面積)。晶片中的低雜訊放大器可以操作在1.5V的低電壓並且可工作在三種不同的增益和雜訊指數的模式下，在高增益模式時可以有28.5 dB的功率增益，2.27 dB的雜訊指數；中增益模式時，有23.6 dB的功率增益，2.43 dB的雜訊指數；在低增益模式時，有18.7 dB的功率增益，2.94 dB的雜訊指數。在新的無線通訊系統上，可調整增益的低雜訊放大器可以應用於訊號的處理上，使得系統的效能提昇。另外吉爾伯特混波器可以提供轉換增益(conversion gain) 9 dB，雜訊指數 11.4 dB，以及埠與埠之間隔離度全小於50 dB並且將接收到的射頻訊號1.95GHz降頻到中頻訊號100MHz，然後送到中頻模組作之後的處理。由於低雜訊放大器可以調整增益，所以可以增加混波器的動態範圍，並且可應用到功率控制的使用。

量測的結果顯示，在1.95GHz的頻帶，VGLNA在三種不同的操作模式下，分別有增益13.5 dB、3.1 dB、-4.2 dB，雜訊指數分別為6.83 dB、9.93 dB、14.3 dB，消秏功率43.5 mw。吉爾伯特混波器的量測結果顯示，有2.7 dB 的轉換增益、5 dBm的IIP3、4 dBm的OIP3、消秏功率為27mW。量測的結果展示了可調整增益的功能以及吉爾伯特混波器設計方法的有效性。

In terms of operating frequency, the wireless communication systems can be divided into three main blocks: radio frequency band (RF), intermediate frequency band (IF), and Base Band, respectively. In general, the circuits operating at IF and Base Band are fabricated and designed in digital by CMOS process, but those of RF must be fabricated and designed in analog by GaAs Process. Besides, for impedance matching, the circuit leads inductors in design, but inductors are not appropriate to be used in CMOS process because the loss of substrate of CMOS process inherently is considerable and thus quality factor of inductor is low, and the Spice models form different foundries are different. So the accurate Spice models of active and passive components are very important in design.
To integrate the three blocks, the cost of manufacture, power consumption, and chip size are reduced. Besides, the systems made by the same CMOS process facilitate to modify and integrate other digital systems. It makes mobile phone, personal digital assistant, and notebook more compact and portable. Thus it speeds the production and affects the PC and relative industries very deeply. So accompanied with that the market of wireless communication systems is dramatically growing, the research of RF ICs is very hot.

The development of CMOS RFIC Design lets the fabrication of System On Chip (SOC) consisting of three blocks: radio frequency (RF), intermediate frequency (IF), and base band frequency realizable; therefore, it reduces considerably the cost and speeds mass production. In this thesis, the design and implementation of 1.5V 1.95GHz Variable Gain Low Noise Amplifier (VGLNA) and Gilbert Mixer (GM) by TSMC (Taiwan Semiconductors Manufacture Company) 0.35 um CMOS process are presented. There are three operating mode of the VGLNA: high gain (28.5dB), medium gain (23.5dB), and low gain (18.5dB) with noise figure all less than 3 dB. The Gilbert Mixer is also operating in 1.5V 1.95GHz with conversion gain 9 dB, noise figure 11.4 dB, and isolation greater than 30dB. It converts down the RF signal 1.95GHz of VGLNA to IF signal 100MHz. The total chip area is 1434 x 1465 um2. The chip can be applied in increase the dynamic range of mixer and power control.

The measurement of the VGLNA shows 13.5 dB, 3.1, -4.2 dB gain and 6.83 dB, 9.93 dB, 14.3 dB noise figure with 43.5 mW power consumption in three modes. The measurement of the Gilbert mixer presents 2.7 dB conversion gain, 5 dBm IIP3, 4 dBm OIP3 with 27 mW power consumption. The measurement of the chip shows that the function behavior of the VGLNA and Gilbert mixer is carried out.

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